參數(shù)資料
型號(hào)： ISPPAC-CLK5620V-01TN48C
廠商： Lattice Semiconductor Corporation
英文描述： LED Area Light; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:630nm
中文描述： 在系統(tǒng)可編程，零延遲時(shí)鐘發(fā)生器通用扇出緩沖器
文件頁(yè)數(shù)： 21/47頁(yè)
文件大小： 871K
代理商： ISPPAC-CLK5620V-01TN48C
Lattice Semiconductor
ispClock5600 Family Data Sheet
21
Differential HSTL and SSTL
HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory
systems. Figure 16 shows how ispClock5600 reference input should be con
fi
gured for accepting these standards.
The major difference between differential and single-ended forms of these logic standards is that in the differential
case, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are
engaged and set to 50
.
Figure 16. Differential HSTL/SSTL Receiver Configuration
LVDS/Differential LVPECL
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50
. The associated REFVTT or FBKVTT pin, however, should be left unconnected. This cre-
ates a
fl
oating 100
differential termination resistance across the input terminals. The LVDS termination con
fi
gura-
tion is shown in Figure 17.
Figure 17. LVDS Input Receiver Configuration
50
CLOSED
REFA-
REFA+
REFVTT
Differential
Receiver
+Signal In
ispClock5600
CLOSED
-Signal In
50
VTT
50
CLOSED
REFA-
REFA+
REFVTT
Differential
Receiver
+Signal In
CLOSED
-Signal In
50
No Connect
LVDS
Driver
ispClock5600
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5610V-01TN48I Backlight LED; Color:Red; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
ISPPAC-CLK5620V-01TN48I Backlight LED; Color:Red; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
ISPPAC-POWR1014 In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ISPPAC-POWR1014-01T48I In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ISPPAC-POWR1014-01TN48I In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPAC-CLK5620V-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-POWR1014 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ISPPAC-POWR1014_08 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ispPAC-POWR1014-01T48I 功能描述:監(jiān)控電路 Prec. Prog. Pwr Sppl y Seq. Mon. Trim I RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPAC-POWR1014-01TN148I 制造商:Lattice Semiconductor Corporation 功能描述:#WR MGR ISP RESET & SEQ CNTRL 48TQFP
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