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參數(shù)資料
| 型號： | ISPPAC-CLK5610V-01TN48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Backlight LED; Color:Red; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| 中文描述： | 5600 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 1/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5610V-01TN48I |
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www.latticesemi.com
1
clk5600_01
November 2004
Preliminary Data Sheet
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci
fi
cations and information herein are subject to change without notice.
ispClock 5600 Family
In-System Programmable, Zero-Delay Clock Generator
with Universal Fan-Out Buffer
Features
■
10MHz to 320MHz Input/Output Operation
■
Low Output to Output Skew (<50ps)
■
Low Jitter Peak-to-Peak (<60ps)
■
Up to 20 Programmable Fan-out Buffers
Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
Programmable output impedance
- 40 to 70
in 5
increments
Programmable slew rate
Up to 10 banks with individual V
CCO
and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■
Fully Integrated High-Performance PLL
Programmable lock detect
Multiply and divide ratio controlled by
- Input divider (5 bits)
- Feedback divider (5 bits)
- Five output dividers (5 bits)
Programmable On-chip Loop Filter
■
Precision Programmable Phase Adjustment
(Skew) Per Output
16 settings; minimum step size 195ps
- Locked to VCO frequency
Up to +/- 12ns skew range
Coarse and
fi
ne adjustment modes
■
■
Up to Five Clock Frequency Domains
Flexible Clock Reference and External
Feedback Inputs
Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
Clock A/B selection multiplexer
Feedback A/B selection multiplexer
Programmable termination
■
Four User-programmable Pro
fi
les Stored in
E
CMOS
Memory
Supports both test and multiple operating
con
fi
gurations
■
Full JTAG Boundary Scan Test In-System
Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
100-pin and 48-pin TQFP Packages
Applications
Circuit board common clock generation and
distribution
PLL-based frequency generation
High fan-out clock buffer
Zero-delay clock buffer
■
■
■
■
Product Family Block Diagram
VCO
OUTPUT
DRIVERS
SKEW
CONTROL
C
R
I
JTAG
INTERFACE
&
E
2
CMOS
MEMORY
LOCK DETECT
FILTER
PHASE/
FREQUENCY
DETECTOR
1
0
2
3
Multiple Profile
Management Logic
INTERNAL FEEDBACK PATH
PLL CORE
OUTPUT
ROUTING
MATRIX
V0
V1
V2
V3
V4
OUTPUT
DIVIDERS
*
*
* Input Available only on ispClock5620
BYPASS
MUX
F
I
Internal/External
Feedback
Select
M
N
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5620V-01TN48I | Backlight LED; Color:Red; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No |
| ISPPAC-POWR1014 | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014-01T48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014-01TN48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014A | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispPAC-CLK5620AV-01T100C | 功能描述:時(shí)鐘驅(qū)動器及分配 ISP 0 Delay Clock Ge n w/Unv Fan-Out Buf RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5620AV-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ispPAC-CLK5620AV-01T100I | 功能描述:時(shí)鐘驅(qū)動器及分配 ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5620AV-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5620AV-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
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