參數(shù)資料
型號: ISPPAC-CLK5620V-01TN100I
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: Backlight LED; Color:Infrared; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No
中文描述: 5600 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100
封裝: LEAD FREE, TQFP-100
文件頁數(shù): 11/47頁
文件大小: 871K
代理商: ISPPAC-CLK5620V-01TN100I
Lattice Semiconductor
ispClock5600 Family Data Sheet
11
Timing Speci
fi
cations
Skew Matching
Programmable Skew Control
Control Functions
Figure 6. RESET and Profile Select Timing
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
t
SKEW
Output-output Skew
Between any two identically con
fi
gured and loaded
outputs regardless of bank.
50
ps
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
t
SKRANGE
Skew Control Range
1
Fine Skew Mode, f
VCO
= 320 MHz
Fine Skew Mode, f
VCO
= 640 MHz
Coarse Skew Mode, f
VCO
= 320 MHz
Coarse Skew Mode, f
VCO
= 640 MHz
5.86
ns
2.93
11.72
5.86
SK
STEPS
Skew Steps per range
16
t
SKSTEP
Skew Step Size
2
Fine Skew Mode, f
VCO
= 320 MHz
Fine Skew Mode, f
VCO
= 640 MHz
Coarse Skew Mode, f
VCO
= 320 MHz
Coarse Skew Mode, f
VCO
= 640 MHz
Fine skew mode
390
ps
195
780
390
t
SKERR
Skew Time Error
3
30
ps
Coarse skew mode
50
1. Skew control range is a function of VCO frequency (f
VCO
). In
fi
ne skew mode T
SKRANGE
= 15/(8 x f
VCO
).
In coarse skew mode T
SKRANGE
= 15/(4 x f
VCO
).
2. Skew step size is a function of VCO frequency (f
VCO
). In
fi
ne skew mode T
SKSTEP
= 1/(8 x f
VCO
).
In coarse skew mode T
SKSTEP
= 1/(4 x f
VCO
).
3. Only applicable to outputs with non-zero skew settings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
t
DIS/OE
Delay Time, OEX or OEY to Output Disabled/
Enabled
10
20
ns
t
DIS/GOE
Delay Time, GOE to Output Disabled/Enabled
10
20
ns
t
SUSGATE
Setup Time, SGATE to Output Clock Start/
Stop
PLL Reset Pulse Width
2
Logic Reset Pulse Width
3
3
cycles
1
t
PLL_RSTW
t
RSTW
t
HPS_RST
1. Output clock cycles for the particular output being controlled.
2. Will completely reset PLL.
3. Will only reset digital logic.
1
ms
20
ns
Hold time for RESET past change in PS[0..1]
20
ns
t
HPS_RST
t
PLL_RSTW
PS[0..1]
RESET
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