參數(shù)資料
型號(hào): ISPPAC-CLK5312S-01TN48I
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 42/56頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK PROGRAM BUFFER 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類(lèi)型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:12
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 267MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤(pán)
Lattice Semiconductor
ispClock5300S Family Data Sheet
47
Package Diagrams
48-Pin TQFP (Dimensions in Millimeters)
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
TO THE LOWEST POINT ON THE PACKAGE BODY.
7.
A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
BASE METAL
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
1.
DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
4.
DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
8.
OF THE PACKAGE BY 0.15 MM.
DIMENSIONS.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
6.
SECTION B-B:
3.
1
b
0.22
0.17
b
0.27
0.16
0.23
0.20
0.09
c
c1
0.09
b1
0.17
0.15
0.13
0.20
MAX.
1.60
0.15
0.75
1.45
e
N
L0.45
0.50 BSC
0.60
48
E1
E
D1
D
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
A2
A1
1.35
0.05
SYMBOL
A-
MIN.
1.40
-
NOM.
-
C A-B D
SEE DETAIL "A"
LEAD FINISH
C
SEATING PLANE
A
3.
0.08
c
b
1
c
MC
b
A-B D
3.
D
4X
8.
e
B
3.
E
D
0.20
GAUGE PLANE
A1
0.08 C
AA2
1.00 REF.
L
0.20 MIN.
B
0-7∞
B
H
E1
0.25
0.20
D
A-B
H
D1
SECTION B - B
DETAIL "A"
NOTES:
PIN 1 INDICATOR
1
N
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ISPPACCLK5312S-01TN48I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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