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參數(shù)資料
| 型號： | ISPPAC-CLK5312S-01TN48I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK PROGRAM BUFFER 48TQFP |
| 標準包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
26
Figure 21. Conguration for SSTL2, SSTL3, and HSTL Output Modes
ispClock5300S Congurations
The ispClock5300S device can be congured to operate in four modes. They are:
Zero Delay Buffer Mode
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Non-Zero Delay Buffer mode 1
Non-Zero Delay Buffer Mode 2
The output routing matrix of the ispClock5300S provides up to three independent any-to-any paths from inputs to
outputs:
From any V-Dividers to any output in ZDB mode or PLL Bypass modes
From selected clock via REFSEL pin to any output (note single ended reference clock)
From the other clock not selected by REFSEL pin to any output
Zero Delay Buffer Mode
Figure 22 shows the ispClock5300S device congured to operate in the Zero Delay Buffer mode. The Clock input
can be single ended or differential. Two single ended clocks can be selected by the use of REFSEL pin and if the
input is congured as a differential the REFSEL pin should be connected to GNDD. The input clock then drives the
Phase frequency detector of the PLL. Up to 3 output clock frequencies can be generated from the input reference
clock by the use of V-dividers at the output of PLL. Any V-divider output can be connected to any of the output pins.
However, one of the V-dividers should be used in the feedback path to set the PLL operating frequency. The PLL
can operate with internal or external feedback path.
In this mode, the skew control mechanism is active for all outputs.
Zo=50
Ro : 40 (SSTL)
20 (HSTL, eHSTL)
ispClock5300S
SSTL/HSTL/eHSTL
Mode
SSTL/HSTL/eHSTL
Receiver
VTT
VREF
RT=50
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5312S-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01TN64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01TN64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5316S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5316S-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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