參數(shù)資料
型號： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 75/98頁
文件大小： 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
75 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
No device connected
Port disabled.
If the port has power control, software cannot change the state of the port until it sets the
port power bits. Software must not attempt to change the state of the port until power is
stable on the port; maximum delay is 20 ms from the transition. For bit allocation, see
Table 106
.
[1]
The reserved bits should always be written with the reset value.
Table 106: PORTSC 1, 2 - Port Status and Control 1, 2 register bit allocation
Address: Value read from func2 of address 10h + 64h + (4 x Port Number
1) where Port Number is 1, 2
Bit
31
30
29
Symbol
Reset
0
0
0
Access
R/W
R/W
R/W
Bit
23
22
21
Symbol
reserved
WKOC_E
WKDS
CNNT_E
Reset
0
0
0
Access
R/W
R/W
R/W
Bit
15
14
13
Symbol
reserved
[1]
PO
Reset
0
0
1
Access
R/W
R/W
R/W
Bit
7
6
5
Symbol
SUSP
FPR
OCC
Reset
0
0
0
Access
R/W
R/W
R
28
27
26
25
24
reserved
[1]
0
0
0
0
0
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
WKCNNT_
E
0
R/W
12
PP
0
R/W
4
OCA
0
R
PTC[3:0]
0
0
0
0
R/W
11
R/W
10
R/W
9
R/W
8
PR
0
R
0
ECCS
0
R
LS[1:0]
reserved
[1]
0
R/W
1
ECSC
0
R/W
0
0
R/W
3
PEDC
0
R/W
R/W
2
PED
0
R/W
Table 107: PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
Address: Value read from func2 of address 10h + 64h + (4 x Port Number
1) where Port Number
is 1, 2
Bit
Symbol
Description
31 to 23 reserved
-
22
WKOC_E
Wake on Overcurrent Enable
: Default = 0. Setting this bit enables the port
to be sensitive to overcurrent conditions as wake-up events.
[1]
21
WKDS
CNNT_E
to be sensitive to device disconnects as wake-up events.
[1]
20
WKCNNT
_E
be sensitive to device connects as wake-up events.
[1]
Wake on Disconnect Enable
: Default = 0. Setting this bit enables the port
Wake on Connect Enable
: Default = 0. Setting this bit enables the port to
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