參數(shù)資料
型號(hào)： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 73/98頁
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
73 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
11.3.6
ASYNCLISTADDR register
This 32-bit register contains the address of the next asynchronous queue head to be
executed. If the Host Controller is in 64-bit mode—as indicated by logic 1 in 64AC (bit 0 of
the HCCPARAMS register)—the most significant 32 bits of every control data structure
address comes from the CTRLDSSEGMENT register. Bits 4 to 0 of this register always
return zeros when read. The memory structure referenced by the physical memory pointer
is assumed as 32 B (cache aligned). For bit allocation, see
Table 102
.
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
reserved
[1]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 101: PERIODICLISTBASE - Periodic Frame List Base Address register bit description
Address: Value read from func2 of address 10h + 34h
Bit
Symbol
Description
31 to 12
BA[19:0]
Base Address
: These bits correspond to memory address signals
31 to 12, respectively.
11 to 0
reserved
-
Table 102: ASYNCLISTADDR - Current Asynchronous List Address register bit allocation
Address: Value read from func2 of address 10h + 38h
Bit
31
30
29
Symbol
Reset
0
0
Access
R/W
R/W
R/W
Bit
23
22
21
Symbol
Reset
0
0
Access
R/W
R/W
R/W
Bit
15
14
13
Symbol
LPL[3:0]
Reset
0
0
Access
R/W
R/W
R/W
Bit
7
6
Symbol
Reset
0
0
Access
R/W
R/W
R/W
28
27
26
25
24
LPL[19:12]
0
0
0
0
0
0
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
LPL[11:4]
0
0
0
0
0
0
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
5
reserved
[1]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
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