參數(shù)資料
型號: ISP1562BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 33/98頁
文件大?。?/td> 442K
代理商: ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
33 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
10.2 USB bus states
Reset state —
When the USB bus is in the reset state, the USB system is stopped.
Operational state —
When the USB bus is in the active state, the USB system is
operating normally.
Suspend state —
When the USB bus is in the suspend state, the USB system is
stopped.
Resume state —
When the USB bus is in the resume state, the USB system is operating
normally.
11. USB Host Controller registers
Each Host Controller contains a set of on-chip operational registers that are mapped to
un-cached memory of the system addressable space. This memory space must begin on
a DWord (32-bit) boundary. The size of the allocated space is defined by the initial value in
the Base Address register 0. HCDs must interact with these registers to implement USB
functionality.
After the PCI enumeration driver finishes the PCI device configuration, the new base
address of these memory-mapped operational registers is defined in BAR 0. The HCD
can access these registers by using the address of base address value + offset.
Table 41
contains a list of Host Controller registers.
Table 41:
Address
USB Host Controller registers
OHCI register
Reset value
[1]
Func0
OHCI1 (1P)
0000 0
010
h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 2EDFh
0000 0000h
0000 0000h
0000 0000h
0000 0628h
FF00 0901
h
EHCI register
Reset value
[1]
Func2
EHCI (2P)
0100 0020
h
0000 2192
h
0000 0012
h
0000 0010
h
0000 0000
h
-
-
-
0008 0000h
0000 1000h
0000 0000h
0000 0000h
-
0000 0000h
0000 0000h
-
-
-
-
Func1
OHCI2 (1P)
0000 0
010
h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 2EDFh
0000 0000h
0000 0000h
0000 0000h
0000 0628h
FF00 0901
h
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
CAPLENGTH/HCIVERSION
HCSPARAMS
HCCPARAMS
HCSP-PORTROUTE1[31:0]
HCSP-PORTROUTE2[59:32]
reserved
reserved
reserved
USBCMD
USBSTS
USBINTR
FRINDEX
reserved
PERIODICLISTBASE
ASYNCLISTADDR
reserved
reserved
reserved
reserved
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