參數(shù)資料
型號： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 53/98頁
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
53 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
11.1.18
HcLSThreshold register
This register contains an 11-bit value used by the Host Controller to determine whether to
commit to the transfer of a maximum of 8 B low-speed packet before EOF. Neither the
Host Controller nor the HCD can change this value. For bit allocation, see
Table 76
.
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
P_S[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 75:
Address: Value read from func0 or func1 of address 10h + 40h
Bit
Symbol
Description
31 to 14
reserved
-
13 to 0
P_S[13:0]
PeriodicStart
: After a hardware reset, this field is cleared. It is then set
by the HCD during the Host Controller initialization. The value is roughly
calculated as 10 % of HcFmInterval. A typical value is 3E67h. When
HcFmRemaining reaches the value specified, processing of the periodic
lists have priority over control or bulk processing. The Host Controller,
therefore, starts processing the interrupt list after completing the current
control or bulk transaction that is in progress.
HcPeriodicStart - Host Controller Periodic Start register bit description
Table 76:
Address: Value read from func0 or func1 of address 10h + 44h
Bit
31
Symbol
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
Bit
15
Symbol
Reset
0
Access
R/W
Bit
7
Symbol
Reset
0
Access
R/W
HcLSThreshold - Host Controller LS Threshold register bit allocation
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
LST[11:8]
0
0
0
0
1
1
0
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
LST[7:0]
0
1
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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