參數(shù)資料
型號: ISL6741
廠商: Intersil Corporation
英文描述: Flexible Double-Ended Voltage and Current Mode PWM Controllers
中文描述: 靈活的雙端電壓和電流模式PWM控制器
文件頁數(shù): 18/21頁
文件大?。?/td> 507K
代理商: ISL6741
18
Performance
The major performance criteria for the converter are
efficiency, and to a lesser extent, load regulation. Efficiency,
load regulation and line regulation performance are
demonstrated in the following Figures.
As expected, the output voltage varies considerably with line
and load when compared to an equivalent converter with
closed loop feedback. However, for applications where tight
regulation is not required, such as those application that use
downstream DC-DC converters, this design approach is
viable.
Waveforms
Typical waveforms can be found in the following Figures.
Figure 13 shows the output voltage during start up.
Figure 14 shows the output voltage ripple and noise at a 5A
load.
Figures 15 and 16 show the voltage waveforms at the
switching node shared by the upper FET source and the
lower FET drain. In particular, Figure 16 shows near ZVS
operation at 8 A of load when the upper FET is turning off
and the lower FET turning on. There is insufficient energy
stored in the leakage inductance to allow complete ZVS
operation. However, since the energy stored in the node
capacitance is proportional to V
2
, a significant portion of the
energy is still recovered. Figure 17 shows the switching
transition between outputs, OUTA and OUTB during steady
state operation. The deadtime duration of 48.6ns is clearly
shown.
FIGURE 10. EFFICIENCY vs LOAD V
IN
= 48V
t
LOAD CURRENT (A)
E
100
95
90
85
80
75
70
0
1
2
3
4
5
6
7
8
9
FIGURE 11. LOAD REGULATION AT V
IN
= 48V
LOAD CURRENT (A)
O
12.5
12.25
12
11.75
11.5
11.25
11
0
1
2
3
4
5
6
7
8
9
FIGURE 12. LINE REGULATION AT I
OUT
= 1A
INPUT VOLTAGE (V)
45
46
47
48
49
50
51
52
53
54
14
13.5
13
12.5
12
11.5
11
O
FIGURE 13. OUTPUT SOFT START
FIGURE 14. OUTPUT RIPPLE AND NOISE - 20 MHz BW
ISL6740, ISL6741
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