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參數資料
| 型號： | ISL6741 |
| 廠商： | Intersil Corporation |
| 英文描述： | Flexible Double-Ended Voltage and Current Mode PWM Controllers |
| 中文描述： | 靈活的雙端電壓和電流模式PWM控制器 |
| 文件頁數： | 13/21頁 |
| 文件大?。?/td> | 507K |
| 代理商： | ISL6741 |
13
produce different designs when presented with identical
requirements. The iterative design process is not presented
here for clarity.
The abbreviated design process follows:
Select a core geometry suitable for the application.
Constraints of height, footprint, mounting preference,
and operating environment will affect the choice.
Determine the turns ratio.
Select suitable core material(s).
Select maximum flux density desired for operation.
Select core size. Core size will be dictated by the
capability of the core structure to store the required
energy, the number of turns that have to be wound, and
the wire gauge needed. Often the window area (the
space used for the windings) and power loss determine
the final core size.
Determine maximum desired flux density. Depending
on the frequency of operation, the core material
selected, and the operating environment, the allowed
flux density must be determined. The decision of what
flux density to allow is often difficult to determine
initially. Usually the highest flux density that produces
an acceptable design is used, but often the winding
geometry dictates a larger core than is indicated based
on flux density alone.
Determine the number of primary turns.
Select the wire gauge for each winding.
Determine winding order and insulation requirements.
Verify the design.
For this application we have selected a planar structure to
achieve a low profile design. A PQ style core was selected
because of its round center leg cross section, but there are
many suitable core styles available.
Since the converter is operating open loop at nearly 100%
duty cycle, the turns ratio, N, is simply the ratio of the input
voltage to the output voltage divided by 2.
The factor of 2 divisor is due to the half-bridge topology.
Only half of the input voltage is applied to the primary of the
transformer.
A PC44HPQ20/6 “E-Core” plus a PC44PQ20/3 “I-Core” from
TDK were selected for the transformer core. The ferrite
material is PC44.
The core parameter of concern for flux density is the
effective core cross sectional area, Ae. For the PQ core
pieces selected:
Ae = 0.62cm
2
or 6.2e -5m
2
Using Faraday’s Law, V = N d
Φ
/dt, the number of primary
turns can be determined once the maximum flux density is
set. An acceptable Bmax is ultimately determined by the
allowable power dissipation in the ferrite material and is
influenced by the lossiness of the core, core geometry,
operating ambient temperature, and air flow. The TDK
datasheet for PC44 material indicates a core loss factor of
~400 mW/cm
3
with a ± 2000 gauss 100kHz sinusoidal
excitation. The application uses a 235kHz square wave
excitation, so no direct comparison between the application
and the data can be made. Interpolation of the data is
required. The core volume is approximately 1.6cm
3
, so the
estimated core loss is
1.28W of dissipation is significant for a core of this size.
Reducing the flux density to 1200 gauss will reduce the
dissipation by about the same percentage, or 40%.
Ultimately, evaluation of the transformer’s performance in
the application will determine what is acceptable.
From Faraday’s Law and using 1200 gauss peak flux density
(
B = 2400 gauss or 0.24 tesla)
Rounding up yields 4 turns for the primary winding. The peak
flux density using 4 turns is ~1100 gauss. From EQ. 1, the
number of secondary turns is 2.
The volts/turn for this design ranges from 5.4V at V
IN
= 43V
to 6.6V at V
IN
= 53V. Therefore, the synchronous rectifier
(SR) windings may be set at 1 turn each with proper FET
selection. Selecting 2 turns for the synchronous rectifier
windings would also be acceptable, but the gate drive losses
would increase.
FIGURE 7. TRANSFORMER SCHEMATIC
n
P
n
SR
n
S
n
S
n
SR
N
V
OUT
2
------------------------
2
---------------
2
=
=
=
(EQ. 14)
P
loss
cm
3
-----------
cm
3
f
meas
---------------
0.4
1.6
---------------------
1.28
=
=
≈
W
(EQ. 15)
N
V
T
B
e
-----------------------------
6
–
2
6.2
10
0.24
----------------------------------------------------
3.56
=
=
=
turns
(EQ. 16)
ISL6740, ISL6741
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISL6741IB | 功能描述:電流型 PWM 控制器 CUR PWM MODE CNTRLR 16LD N RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6741IB-T | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產品目錄頁面:1316 (CN2011-ZH PDF) |
| ISL6741IBZ | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6741IBZ-T | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6741IV | 功能描述:IC REG CTRLR PWM CM 16-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產品目錄頁面:1316 (CN2011-ZH PDF) |
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