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參數(shù)資料
| 型號： | ISL6741 |
| 廠商： | Intersil Corporation |
| 英文描述： | Flexible Double-Ended Voltage and Current Mode PWM Controllers |
| 中文描述： | 靈活的雙端電壓和電流模式PWM控制器 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 507K |
| 代理商： | ISL6741 |
10
where T
C
and T
D
are the charge and discharge times,
respectively, T
SW
is the oscillator free running period, and f
is the oscillator frequency. One output switching cycle
requires two oscillator cycles. The actual times will be
slightly longer than calculated due to internal propagation
delays of approximately 10ns/transition. This delay ads
directly to the switching duration, but also causes overshoot
of the timing capacitor peak and valley voltage thresholds,
effectively increasing the peak-to-peak voltage on the timing
capacitor. Additionally, if very low charge and discharge
currents are used, there will be increased error due to the
input impedance at the C
T
pin.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
Implementing Synchronization
The oscillator can be synchronized to an external clock
applied to the SYNC pin or by connecting the SYNC pins of
multiple ICs together. If an external master clock signal is
used, the free running frequency of the oscillator should be
~10% slower than the desired synchronous frequency. The
external master clock signal should have a pulse width
greater than 20ns. The SYNC circuitry will not respond to an
external signal during the first 60% of the oscillator switching
cycle.
The SYNC input is edge triggered and its duration does not
affect oscillator operation. However, the deadtime is affected
by the SYNC frequency. A higher frequency signal applied to
the SYNC input will shorten the deadtime. The shortened
deadtime is the result of the timing capacitor charge cycle
being prematurely terminated by the external SYNC pulse.
Consequently, the timing capacitor is not fully charged when
the discharge cycle begins. This effect is only a concern
when an external master clock is used, or if units with
different operating frequencies are paralleled.
Soft Start Operation
The ISL6740, ISL6741 feature a soft start using an external
capacitor in conjunction with an internal current source. Soft
start reduces stresses and surge currents during start up.
Upon start up, the soft start circuitry clamps the error voltage
input (V
ERROR
pin) indirectly to a value equal to the soft
start voltage. The soft start clamp does not actually clamp
the error voltage input as is done in many implementations.
Rather the PWM comparator has two inverting inputs such
that the lower voltage is in control.
The output pulse width increases as the soft start capacitor
voltage increases. This has the effect of increasing the duty
cycle from zero to the regulation pulse width during the soft
start period. When the soft start voltage exceeds the error
voltage, soft start is completed. Soft start occurs during
start-up, after recovery from a Fault condition or over
current/short circuit shutdown. The soft start voltage is
clamped to 4.5V.
Gate Drive
The ISL6740, ISL6741 are capable of sourcing and sinking
0.5A peak current, but are primarily intended to be used in
conjunction with a MOSFET driver due to the 5V drive level.
To limit the peak current through the IC, an external resistor
may be placed between the totem-pole output of the IC
(OUTA or OUTB pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.
Under Voltage Monitor and Inhibit
The UV input is used for input source under voltage lockout
and inhibit functions. If the node voltage falls below 1.00V a
UV shutdown fault occurs. This may be caused by low
source voltage or by intentional grounding of the pin to
disable the outputs. There is a nominal 10
μ
A switched
current source used to create hysteresis. The current source
is active only during an UV/Inhibit fault; otherwise, it is
inactive and does not affect the node voltage. The
magnitude of the hysteresis is a function of the external
resistor divider impedance. If the resistor divider impedance
results in too little hysteresis, a series resistor between the
UV pin and the divider may be used to increase the
hysteresis. A soft start cycle begins when the UV/Inhibit fault
clears.
D
T
SW
------------
=
(EQ. 5)
DT
1
D
–
=
(EQ. 6)
ISL6740, ISL6741
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6741IB | 功能描述:電流型 PWM 控制器 CUR PWM MODE CNTRLR 16LD N RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6741IB-T | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產(chǎn)品目錄頁面:1316 (CN2011-ZH PDF) |
| ISL6741IBZ | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6741IBZ-T | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6741IV | 功能描述:IC REG CTRLR PWM CM 16-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產(chǎn)品目錄頁面:1316 (CN2011-ZH PDF) |
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