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參數(shù)資料
| 型號(hào)： | ISL6721 |
| 廠商： | Intersil Corporation |
| 英文描述： | Flexible Single Ended Current Mode PWM Controller(靈活的單端電流模式PWM控制器) |
| 中文描述： | 靈活的單端電流模式PWM控制器（靈活的單端電流模式的PWM控制器） |
| 文件頁數(shù)： | 16/21頁 |
| 文件大小： | 416K |
| 代理商： | ISL6721 |
16
FN9110.5
July 20, 2007
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
precaution in case operation in continuous mode should
occur at some operating point.
Development of a small signal model for current mode
control is rather complex. The method of reference [1] was
selected for its ability to accurately predict loop behavior. To
further simplify the analysis, the converter will be modeled as
a single output supply with all of the output capacitance
reflected to the 3.3V output. Once the “single” output system
is compensated, adjustments to the compensation will be
required based on actual loop measurements.
feedback loop gain. Since this application is low power, a
resistor in series with the source of the power switching
MOSFET is used for the current feedback signal. For higher
power applications, a resistor would dissipate too much
power and current transformer would be used instead.
There is limited flexibility to adjust the current loop behavior
due to the need to provide overcurrent protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
determining ISET, the internal gain and offset of the ISENSE
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
limit is reasonable. A current gain, A
EXT
, of 0.5V/A was
selected to achieve this.
The control to output transfer function may be represented
as [2]
z
s
ω
p
if we ignore the current feedback sampled-data effects.
I
)
c max
)
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
determined earlier as 15W, so
where A
EXT
is the external gain of the current feedback
network, A
CS
is the IC internal gain, and A
COMP
is the gain
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the “Typical Application - 48V Input
Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A” on page 3,
the remaining pole and zero for the compensator are located
at:
C
2
15
The ratio of R
15
to the parallel combination of R
17
and R
18
determine the mid band gain of the error amplifier.
From Equation 27, it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
FIGURE 8. TYPE 2 ERROR AMPLIFIER
REF
+
-
V
OUT
V
ERROR
ISET
2.25
0.8
0.5
0.100
+
1.00
=
=
V
(EQ. 26)
v
o
v
c
-----
K
R
---------------------------------
L
f
1
----------------
------
+
1
------
+
=
(EQ. 27)
K
-------------------------
=
(EQ. 28)
R
o
LoadResis
ce
tan
=
(EQ. 29)
L
s
SecondaryInduc
ce
tan
=
(EQ. 30)
ω
p
o
o
--------------------
=
or
f
p
o
o
-----------------------------
=
(EQ. 31)
ω
z
c
o
-------------------
=
or
f
z
c
o
--------------------------------------
=
(EQ. 32)
C
o
OutputCapaci
ce
tan
=
(EQ. 33)
R
c
OutputCapaci
ceE
tan
SR
=
(EQ. 34)
V
c max
)
ControlVoltageRange
=
(EQ. 35)
I
spk max
)
2
--------------------------------------
P
-----------
Tsw
2
-----------------------------------------
-------
5
6
–
×
10
2.33
×
10
19.5
=
=
=
A
(EQ. 36)
v
c max
)
V
ISENSE
A
EXT
A
CS
COMP
--------------------
2.93
=
=
V
(EQ. 37)
f
pc
C
14
+
13
------------------------------------------------------------
15
14
--------------------------------------------
≈
=
(EQ. 38)
f
zc
15
13
--------------------------------------------
=
(EQ. 39)
A
midband
R
-----------------------------------------------
R
R
+
(
)
17
18
=
(EQ. 40)
ISL6721
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