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參數(shù)資料
| 型號： | ISL5217KIZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, LEAD FREE, PLASTIC, BGA-196 |
| 文件頁數(shù)： | 6/43頁 |
| 文件大?。?/td> | 797K |
| 代理商： | ISL5217KIZ |
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6
FN6004.3
July 8, 2005
Functional Description
The ISL5217 Quad Programmable UpConverter (QPUC)
converts digital baseband data into modulated or frequency
translated digital samples. The QPUC can be configured to
create any quadrature amplitude shift-keyed (QASK) data
modulated signal, including QPSK, BPSK, and m-ary QAM.
The QPUC can also be configured to create both shaped
and unfiltered FM signals. A minimum of 16 bits of resolution
is maintained throughout the internal processing.
The QPUC is configured via the microprocessor data bus,
using the A<6:0> address bus, P<15:0> data bus, RD, WR
and CS control signals. Configuration data that is loaded via
this bus includes the individual channel’s 48-bit Sample Rate
NCO center frequency, the 32-bit Carrier NCO center
frequency, the device modulation format, gain control, input
mode control, reset control and sync control. The I and Q
baseband channels each have a 256 tap FIR filter whose
coefficients and configuration are also programmed via the
μ
P interface. Similarly, the control signals for the I and Q
channel interpolation filters are programmed via the
μ
P
interface. Discussion in the following sections utilizes the
register definitions for channel 0. Channels 1-3 are similarly
configured in accordance with the Table 10 Memory Map.
Data Input
The I/Q sample pairs can be input serially through 1 of 4
serial interfaces or in parallel through the
μ
P addressable
registers as shown in Figure 1.
Serial
The serial mode allows the device to shift the I and Q samples
serially into the FIFO holding registers. The serial input format
is selected when Serial control (0x11, bit 15) is high. The serial
interface is three-wire interface controlled by the channel. The
serial clock and frame strobe are driven by the channel to clock
the serial data from the source into the serial data port. The
serial clock can operate at the clock rate, at a divided clock rate,
or be driven at 32x the sample clock rate. Serial control (0x11,
bits 13:8) configure the serial clock. In the 32x mode, back to
back 16-bit serial transfers can occur by setting control word
(0x17, bits 14:13) both high. The serial process begins with the
first serial clock after the start of a sample clock. The frame
strobe is asserted for one serial clock and starts the I and Q
time slot counters. The TXENX pin or Main control (0X0c, bit 0)
S/W TX enable must be asserted to enable the frame strobe
out. Additional requests for serial data, with TXENX de-
asserted, are controlled by bit 3 of control word 0x0c. The serial
interface may be programmed to be dependent or independent
of TXENX control. The I and Q time slot counters, programmed
through 0x12, bits 9:0 and 0x13, bits 9:0, control the duration of
the serial to parallel conversion of the serial data input. The
counters are loaded to count the number of serial clocks from
the frame strobe to shift in the last data bit of that sample. The
time slot counters are 10-bits to allow multiple channels to
share a common serial data input. The MSB is always shifted
first, but the order of the I and Q serial data is flexible due to the
variability of the time slot counters. The received serial word is
MSB justified prior to loading into the FIFO holding register
based on the serial word length, programed through Serial
control (0x11, bits 3:2) to 4, 8, 12, or 16 bits.
Although each channel has control of a serial interface it may
select serial data from one of the other interfaces. Serial
control (0x11, bits 1:0) selects 1 of 4 serial data ports for the
channel. The serial data transfer format is shown in Figure 2.
The ability to select the serial input source allows multiple
QPUCs to share a single microprocessor interface with their
processing synchronized through the master QPUC SYNCO
being tied to the slave device UPDX. Conversely, multiple
FIGURE 1. SINGLE CHANNEL DATA INPUT PATH
4
SDB
SDC
SDD
SDA
2
0x11, 1:0
S
P
0x13, 9:0
0x12, 9:0
2
Q sample (15:0)
I sample (15:0)
0x1, 15:0
0x0, 15:0
P<15:0>
A<6:0>
0x11, 15
C
μ
0x11, 3:2
P
FIGURE 2. SERIAL DATA TRANSFER
UPDX
TXENX
FSRBX
SDX
SCLKX
INACTIVE
DON’T CARE
Q
Q
I
I
ISL5217
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