參數(shù)資料
型號(hào)： ISL5217KIZ
廠商： INTERSIL CORP
元件分類： 無繩電話/電話
英文描述： Quad Programmable Up Converter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： 15 X 15 MM, LEAD FREE, PLASTIC, BGA-196
文件頁數(shù)： 39/43頁
文件大?。?/td> 797K
代理商： ISL5217KIZ
39
FN6004.3
July 8, 2005
7
Sync Out Polarity
Sync out polarity
0 = defines a sync assertion as a transition from a logic low to a logic high.
1 = defines a sync assertion as a transition from a logic high to a logic low.
6
Output Enable
Enables data out of the device. Zeroes the data when low.
5
I Strobe Enable
Indicates when I data is output in the muxed I/Q mode.
4
I Strobe Polarity
I strobe polarity.
0 = defines a sync assertion as a transition from a logic low to a logic high. (I out when low)
1 = defines a sync assertion as a transition from a logic high to a logic low. (I out when high)
3
Cascade Input Enable
Enables I and Q cascade data into the device. Zeroes the input buses when low. Set to zero when using
any mode other than Cascade.
2:1
Cascade Delay (1:0)
Delays the 4 Ch sum to align with the cascade input summer. A cascade of 4 devices is supported.
00 = No Delay for master.
01 = Delay for first slave.
10 = Delay for second slave.
11 = Delay for last slave.
0
Broadcast
Enables all four channels to receive current
μ
P write access.
NOTES:
37. There is also a complex output mode available for 4-ch summers 1 and 3 when the cascade feature is not required. This is accomplished by
setting the output mode to 0x01 in the top control register and selecting the complex output mode in the main control register of channel 0 or
channel 2. This mode allows I and Q data to be clocked out in parallel at the full rate. Refer to the Main Control register for further detail.
38. The cascade input of the first device in a cascade chain must be disabled.
TABLE 45. DEVICE CONTROL (Continued)
TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x78
BIT
FUNCTION
DESCRIPTION
0 =
1 =
0 =
1 =
I
Q
I
I
Q
Q
TABLE 46. DEVICE OUTPUT ROUTING
TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x79
OUTPUT MODE
REAL,
IMAG, or
MUXED
BIT
FUNCTION
DESCRIPTION
CASCADE
COMPLEX
1
COMPLEX
2
COMPLEX
3
15
Channel 3 Routing Routes channel 3 output to output summer 4.
X
X
14
Channel 3 Routing Routes channel 3 output to output summer 3.
X
X
X
X
13
Channel 3 Routing Routes channel 3 output to output summer 2.
X
X
12
Channel 3 Routing Routes channel 3 output to output summer 1.
X
X
X
X
X
11
Channel 2 Routing Routes channel 2 output to output summer 4.
X
X
10
Channel 2 Routing Routes channel 2 output to output summer 3.
X
X
X
X
9
Channel 2 Routing Routes channel 2 output to output summer 2.
X
X
8
Channel 2 Routing Routes channel 2 output to output summer 1.
X
X
X
X
X
7
Channel 1 Routing Routes channel 1 output to output summer 4.
X
X
6
Channel 1 Routing Routes channel 1 output to output summer 3
X
X
X
X
5
Channel 1 Routing Routes channel 1 output to output summer 2
X
X
4
Channel 1 Routing Routes channel 1 output to output summer 1
X
X
X
X
X
3
Channel 0 Routing Routes channel 0 output to output summer 4
X
X
ISL5217
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