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參數(shù)資料
| 型號(hào)： | ISL5217KIZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, LEAD FREE, PLASTIC, BGA-196 |
| 文件頁數(shù)： | 29/43頁 |
| 文件大?。?/td> | 797K |
| 代理商： | ISL5217KIZ |
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29
FN6004.3
July 8, 2005
TABLE 23. CARRIER PHASE OFFSET (15:0)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x07
BIT
FUNCTION
DESCRIPTION
15:0
Carrier Phase Offset
Initializes the most-significant 16-bits of the phase accumulator. The carrier phase offset is computed by
the formula:
Carrier Phase Offset (15:0) = INT [(Phase Offset 0 / 3600 * 2
32
)) /216]
TABLE 24. CARRIER FREQUENCY (31:16) MSW
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x08
BIT
FUNCTION
DESCRIPTION
15:0
Carrier NCO
CF(31:16) is loaded in this address.
TABLE 25. CARRIER FREQUENCY (15:0) LSW
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x09
BIT
FUNCTION
DESCRIPTION
15:0
Carrier NCO
CF(15:0) is loaded in this address. The SIN/COS generator is controlled by a 32-bit NCO clocked at the
output clock rate. The center frequency is computed by the formula:
f
C = CF(31:0) x fCLK x 2-32; CF(31:0) = INT(fC/fCLK X 232).
NOTE: Writing to the LSW generates the update strobe to load the slave configuration reg when in the immediate mode
TABLE 26. GAIN
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0a
BIT
FUNCTION
DESCRIPTION
15
Reserved
Not Used.
14:12
Step Atten (2:0)
Select 1 of 8 fixed attenuations
000 - scale by 4096
001 - scale by 256
010 - scale by 32
011 - scale by 16
100 - scale by 8
101 - scale by 4
110 - scale by 2
111 - scale by 1
11:0
Unsigned Gain Multiplier
The gain multiplier is computed by the formula:
Gain(11:0) =[10
|(Gain(db)| / 20 )
2
12
]Hex
Bit weight. 2
-1
2
-2
... 2
-12
Maximum 0xFFF = 1.0 - 2-12
=0.9998
0x800 = 0.5
0x001 = 2
-12
Minimum 0x000 = 0.0
TABLE 27. GAIN PROFILE
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0b
BIT
FUNCTION
DESCRIPTION
8:7
Gain Profile Latency
Set bit 7 high to remove two edge latencies from the delay path. This should be combined DS=3, IP=4
settings to provide perfect symmetry through the gain block. Set bit 8 high to bypass all latency alignment
circuitry and to use TXENX as input to the channel.
6:0
Gain Profile Length
Set to the upper address used for the gain profile RAM.
ISL5217
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