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參數(shù)資料
| 型號(hào)： | ISL51002 |
| 廠商： | Intersil Corporation |
| 英文描述： | 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features(具有測(cè)量和音頻調(diào)節(jié)功能的10-Bit視頻模擬前端(AFE)) |
| 中文描述： | 10位的測(cè)量和自動(dòng)視頻模擬前端（AFE）調(diào)整功能（具有測(cè)量和音頻調(diào)節(jié)功能的10位視頻模擬前端（AFE）的） |
| 文件頁數(shù)： | 25/32頁 |
| 文件大小： | 360K |
| 代理商： | ISL51002 |
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25
FN6164.2
September 19, 2007
Intersil’s DPLL has the capability to correct large phase
changes almost instantly by maximizing the phase error gain
while keeping the frequency gain relatively low. This is done
by changing the contents of register 0x74 to 0x4C. This
increases the phase error gain to 100%. Because a phase
setting this high will slightly increase jitter, the default setting
(0x49) for register 0x74 is recommended for all other sync
sources.
SYNC Timing Measurement
The ISL51002 analyzes the timing characteristics of the
sysnc signals for the currently selected input channel and
presents the results in registers 0x40 through 0x0x46.
The HSYNC period and pulse width values are 16-bit
numbers representing the number of crystal clocks in 16
consecutive periods or pulse widths giving a measurment
resolution of 1/16th of a crystal clock.
The VSYNC period is a 12-bit number representing the
number of either HSYNCs or units of 512 crystal clocks that
occure in one video frame. The default is to count HSYNC
pulses but setting register 0x4F[0] = 1 changes to the units
to crystal clock ÷ 512.
The VSYNC pulse width is a 12-bit number representing the
number of either HSYNCs or units of 512 crystal clocks that
occure in one VSYNC. The default is to count HSYNC
pulses but setting register 0x4F[0] = 1 changes to the units
to crystal clock ÷ 512.
PGA
The ISL51002’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is:
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1V/V, the GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per
line. In normal operation this means that there is a maximum
delay of one HSYNC period between a write to a Gain
register for a particular color and the corresponding change
in that channel’s actual PGA gain. If there is no regular
HSYNC/SOG source, or if the external clamp option is
enabled (register 0x10[7:6]) but there is no external clamp
signal being generated, it may take up to 100ms for a write
to the Gain register to update the PGA. This is not an issue
in normal operation with RGB and YPbPr signals.
Offset DAC
The ISL51002 features a 10-bit Digital-to-Analog Converter
(DAC) to provide extremely fine control over the full channel
offset. The DAC is placed after the PGA to eliminate
interaction between the PGA (controlling “contrast”) and the
Offset DAC (controlling “brightness”).
In normal operation, the Offset DAC is controlled by the
ABLC circuit, ensuring that the offset is always reduced
to sub-LSB levels (See the following ABLC section for
more information). When ABLC is enabled, the Offset
register pairs (0x18 and 0x19 through 0x1C and 0x1D)
control a digital offset added to or subtracted from the
output of the ADC. This mode provides the best image
quality and eliminates the need for any offset calibration.
If desired, ABLC can be disabled (0x27[0] = 1) and the
Offset DAC programmed manually, with the 8 most
significant bits in registers 0x18, 0x1A,10x1C, and the 2
least significant bits in registers 0x19[7:6], 0x1B[7:6] and
0x1D[7:6].
-
+
GREEN
SLICER DAC
600mV TO 900mV
+
–
600mV
SOG
IN
1
μ
A
4
R
IN
C
IN
10nF
500
CLAMP
SLICE
FILTER
ON/OFF
HIST
ON/OFF
-
+
SYNCOUT
FIGURE 2. SOG SLICER
Ω
GainV
0.5
170
GainCode
+
=
(EQ. 1)
ISL51002
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ISL51002_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| ISL51002CQZ-110 | 功能描述:IC FRONT END 10BIT VID 128-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ISL51002CQZ-150 | 制造商:Intersil Corporation 功能描述:AFE VID 3ADC 10-BIT 1.8V/3.3V 128MQFP EP - Trays 制造商:Intersil 功能描述:10 BIT VID AFE MEASURE&AUTO-ADJUST 制造商:Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| ISL51002CQZ-165 | 功能描述:IC FRONT END 10BIT VID 128-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ISL51002EVALZ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
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