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參數(shù)資料
| 型號(hào)： | ISL51002 |
| 廠商： | Intersil Corporation |
| 英文描述： | 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features(具有測(cè)量和音頻調(diào)節(jié)功能的10-Bit視頻模擬前端(AFE)) |
| 中文描述： | 10位的測(cè)量和自動(dòng)視頻模擬前端（AFE）調(diào)整功能（具有測(cè)量和音頻調(diào)節(jié)功能的10位視頻模擬前端（AFE）的） |
| 文件頁(yè)數(shù)： | 12/32頁(yè) |
| 文件大?。?/td> | 360K |
| 代理商： | ISL51002 |
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12
FN6164.2
September 19, 2007
0x04
Interrupt Status,
Write a 1 to each bit to clear
it, 0xFF to clear all.
0
CH0 Sync Changed
0: No change
1: CH0 activity or polarity changed
1
CH1 Sync Changed
0: No change
1: CH1 activity or polarity changed
2
CH2 Sync Changed
0: No change
1: CH2 activity or polarity changed
3
CH3 Sync Changed
0: No change
1: CH3 activity or polarity changed
4
Selected Input Channel
Disrupted
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
signal has changed (fast notification of a mode change)
5
Selected Input Channel
Changed
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
period or pulse width has settled to a new value and can be
measured
6
VSYNC INT
0: Default state
1: VSYNC occurred
7
PADJ INT
0: Default state
1: Phase Adjustment function completed.
0x05
Interrupt Mask Register,
(0xFF)
0
CH0 Mask
0: Generate interrupt if CH0 sync activity, polarity, period, or
pulse width changes
1: Mask CH0 interrupt
1
CH1 Mask
0: Generate interrupt if CH1 sync activity, polarity, period, or
pulse width changes
1: Mask CH1 interrupt
2
CH2 Mask
0: Generate interrupt if CH2 sync activity, polarity, period, or
pulse width changes
1: Mask CH2 interrupt
3
CH3 Mask
0: Generate interrupt if CH3 sync activity, polarity, period, or
pulse width changes
1: Mask CH3 interrupt
4
Input Disrupted Mask
0: Generate interrupt if selected Input Channel’s sync inputs
are disrupted
1: Mask Input Channel interrupt
5
Input Changed Mask
0: Generate interrupt after selected Input Channel period or
pulse width settles to new value
1: Mask Input Channel interrupt
6
VSYNC INT Mask
0: Generate interrupt every VSYNC
1: Mask VSYNC Interrupt
7
PADJ INT Mask
0: Generate interrupt upon phase adjustment block request
completion
1: Mask Phase adjustment interrupt
Register Listing
(Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL51002_07 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| ISL51002CQZ-110 | 功能描述:IC FRONT END 10BIT VID 128-MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ISL51002CQZ-150 | 制造商:Intersil Corporation 功能描述:AFE VID 3ADC 10-BIT 1.8V/3.3V 128MQFP EP - Trays 制造商:Intersil 功能描述:10 BIT VID AFE MEASURE&AUTO-ADJUST 制造商:Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| ISL51002CQZ-165 | 功能描述:IC FRONT END 10BIT VID 128-MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ISL51002EVALZ | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
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