Note (1): These 1-byte register values are merely copied by the ISL35822 from the I2
參數(shù)資料
型號： ISL35822LPIK
廠商： Intersil
文件頁數(shù)： 26/75頁
文件大?。?/td> 0K
描述： IC CLOCK/DATA RECOVERY 192EBGA-B
標準包裝： 90
類型： 時鐘和數(shù)據(jù)恢復（CDR），多路復用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.59Gbps
電源電壓： 1.3 V ~ 1.41 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應商設備封裝： 192-EBGA-B（17x17）
包裝： 托盤
32
Note (1): These 1-byte register values are merely copied by the ISL35822 from the I2C address space on Power-up or RESET, or on a periodic or on-demand direct
DOM update operation (i.e. with Register bit 1.C018’h.2 Table 51 not set) under the control of Register 1.A100’h (Table 38). The ISL35822 takes no action as
a result of the values copied.
Note (1): These 1-byte register values are copied by the ISL35822 from the I2C address space on Power-up or RESET, or on any DOM read operation. If the ‘Indirect
DOM Enable’ bit (Register bit 1.C018’h.2 Table 51) is not set, a four-lane external DOM device is expected to determine the values for these registers,
according to Section 11.3 in the XENPAK MSA Rev 3.0 specification. A single one-lane DOM device system will provide the values from the single DOM
device here. If the ‘Indirect DOM Enable’ bit is set, the values from the “Representative” (as set by Register bits 1.C018’h.1:0 in Table 51) lane DOM are
entered here. See “DOM Registers” on page 16. These bits are gated with the enable bits in 1.9006:7 (Table 30 & Table 31) and the LX4/CX4 select
LX4_MODE pin to drive bits 1.9004.1 & 1.9003.1 (Table 28 & Table 27), and if enabled via 1.9002 & 1.9001 (Table 25 & Table 24) to drive the LASI pin.
Table 35. XENPAK DOM EXTENDED CAPABILITY REGISTER
MDIO REGISTER, ADDRESS = 1.41071 (1.A06F’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
1.41071.15:8
Reserved
00’h(1)
1.41071.7
TT_Able
1 = Indicates
Capability
Implemented
0 = Not
Implemented
RO
Transceiver Temp Monitoring Capable
1.41071.6
LBC_Able
RO
Laser Bias Current Monitoring Capable
1.41071.5
LOP_Able
RO
Laser Output Power Monitoring Capable
1.41071.4
ROP_Able
RO
Receive Optical Power Monitoring Capable
1.41071.3
AL_Able
RO
Alarm Flags for Monitored Quantities
1.41071.2
WN_Able
RO
Warning Flags for Monitored Quantities
1.41071.1
MON_LASI
RO
Monitoring Quantities Input to LASI
1.41071.0
Reserved
RO
Monitoring Capable
Table 36. XENPAK DOM ALARM FLAGS REGISTER
MDIO REGISTER, ADDRESS = 1.41072:3 (1.A070:1’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
1.41072.15:8
Reserved
00’h(1)
RO
1.41072.7
TT_High
1 = Alarm Set
0 = Alarm Not Set
0’b
RO
Transceiver Temp High Alarm
1.41072.6
TT_Low
0’b
RO
Transceiver Temp Low Alarm
1.41072.5:4
Reserved
00’b
1.41072.3
LBC_High
1 = Alarm Set
0 = Alarm Not Set
0’b
RO
Laser Bias Current High Alarm
1.41072.2
LBC_Low
0’b
RO
Laser Bias Current Low Alarm
1.41072.1
LOP_High
0’b
RO
Laser Output Power High Alarm
1.41072.0
LOP_Low
0’b
RO
Laser Output Power Low Alarm
1.41073.15:8
Reserved
00’h
1.41073.7
ROP_High
1 = Alarm Set
0 = Alarm Not Set
0’b
RO
Receive Optical Power High Alarm
1.41073.6
ROP_Low
0’b
RO
Receive Optical Power Low Alarm
1.41073.5:0
Reserved
00’h
Table 37. XENPAK DOM WARNING FLAGS REGISTER
MDIO REGISTER, ADDRESS = 1.41076:7 (1.A074:5’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
1.41076.15:8
Reserved
00’h(1)
1.41076.7
TT_High
1 = Warning Set
0 = Warn. Not Set
0’b
RO
Transceiver Temp High Warning
1.41076.6
TT_Low
0’b
RO
Transceiver Temp Low Warning
1.41076.5:4
Reserved
00’b
ISL35822
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