Note (1): These 1-byte register values are merely copied by the ISL35822 from the I2
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ISL35822IK
寤犲晢锛� Intersil
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 26/75闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CLOCK/DATA RECOVERY 192EBGA-B
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
椤炲瀷锛� 鏅�(sh铆)閻樺拰鏁�(sh霉)鎿�(j霉)鎭㈠京(f霉)锛圕DR锛夛紝澶氳矾寰�(f霉)鐢ㄥ櫒
PLL锛� 鐒�(w煤)
杓稿叆锛� CML
杓稿嚭锛� CML锛孋MOS
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 8:8
宸垎 - 杓稿叆:杓稿嚭锛� 鏄�/鏄�
闋荤巼 - 鏈€澶э細 3.1875Gbps
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 192-EBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 192-EBGA-B锛�17x17锛�
鍖呰锛� 鎵樼洡
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32
Note (1): These 1-byte register values are merely copied by the ISL35822 from the I2C address space on Power-up or RESET, or on a periodic or on-demand direct
DOM update operation (i.e. with Register bit 1.C018鈥檋.2 Table 51 not set) under the control of Register 1.A100鈥檋 (Table 38). The ISL35822 takes no action as
a result of the values copied.
Note (1): These 1-byte register values are copied by the ISL35822 from the I2C address space on Power-up or RESET, or on any DOM read operation. If the 鈥業ndirect
DOM Enable鈥� bit (Register bit 1.C018鈥檋.2 Table 51) is not set, a four-lane external DOM device is expected to determine the values for these registers,
according to Section 11.3 in the XENPAK MSA Rev 3.0 specification. A single one-lane DOM device system will provide the values from the single DOM
device here. If the 鈥業ndirect DOM Enable鈥� bit is set, the values from the 鈥淩epresentative鈥� (as set by Register bits 1.C018鈥檋.1:0 in Table 51) lane DOM are
entered here. See 鈥淒OM Registers鈥� on page 16. These bits are gated with the enable bits in 1.9006:7 (Table 30 & Table 31) and the LX4/CX4 select
LX4_MODE pin to drive bits 1.9004.1 & 1.9003.1 (Table 28 & Table 27), and if enabled via 1.9002 & 1.9001 (Table 25 & Table 24) to drive the LASI pin.
Table 35. XENPAK DOM EXTENDED CAPABILITY REGISTER
MDIO REGISTER, ADDRESS = 1.41071 (1.A06F鈥檋)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
1.41071.15:8
Reserved
00鈥檋(1)
1.41071.7
TT_Able
1 = Indicates
Capability
Implemented
0 = Not
Implemented
RO
Transceiver Temp Monitoring Capable
1.41071.6
LBC_Able
RO
Laser Bias Current Monitoring Capable
1.41071.5
LOP_Able
RO
Laser Output Power Monitoring Capable
1.41071.4
ROP_Able
RO
Receive Optical Power Monitoring Capable
1.41071.3
AL_Able
RO
Alarm Flags for Monitored Quantities
1.41071.2
WN_Able
RO
Warning Flags for Monitored Quantities
1.41071.1
MON_LASI
RO
Monitoring Quantities Input to LASI
1.41071.0
Reserved
RO
Monitoring Capable
Table 36. XENPAK DOM ALARM FLAGS REGISTER
MDIO REGISTER, ADDRESS = 1.41072:3 (1.A070:1鈥檋)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
1.41072.15:8
Reserved
00鈥檋(1)
RO
1.41072.7
TT_High
1 = Alarm Set
0 = Alarm Not Set
0鈥檅
RO
Transceiver Temp High Alarm
1.41072.6
TT_Low
0鈥檅
RO
Transceiver Temp Low Alarm
1.41072.5:4
Reserved
00鈥檅
1.41072.3
LBC_High
1 = Alarm Set
0 = Alarm Not Set
0鈥檅
RO
Laser Bias Current High Alarm
1.41072.2
LBC_Low
0鈥檅
RO
Laser Bias Current Low Alarm
1.41072.1
LOP_High
0鈥檅
RO
Laser Output Power High Alarm
1.41072.0
LOP_Low
0鈥檅
RO
Laser Output Power Low Alarm
1.41073.15:8
Reserved
00鈥檋
1.41073.7
ROP_High
1 = Alarm Set
0 = Alarm Not Set
0鈥檅
RO
Receive Optical Power High Alarm
1.41073.6
ROP_Low
0鈥檅
RO
Receive Optical Power Low Alarm
1.41073.5:0
Reserved
00鈥檋
Table 37. XENPAK DOM WARNING FLAGS REGISTER
MDIO REGISTER, ADDRESS = 1.41076:7 (1.A074:5鈥檋)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
1.41076.15:8
Reserved
00鈥檋(1)
1.41076.7
TT_High
1 = Warning Set
0 = Warn. Not Set
0鈥檅
RO
Transceiver Temp High Warning
1.41076.6
TT_Low
0鈥檅
RO
Transceiver Temp Low Warning
1.41076.5:4
Reserved
00鈥檅
ISL35822
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-22Y-MX-S CONVERTER MOD DC/DC 3.3V 49.5W
VI-22Y-MW-S CONVERTER MOD DC/DC 3.3V 66W
MS27474E16B55PA CONN RCPT 55POS JAM NUT W/PINS
V24A24M300BF3 CONVERTER MOD DC/DC 24V 300W
D38999/24KC4SA CONN RCPT 4POS JAM NUT W/SCKT
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