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參數(shù)資料
| 型號： | ISL1219 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Power RTC with Battery Backed SRAM and Event Detection(具有電池供電的SRAM和事件檢測功能的低功率RTC) |
| 中文描述： | 低功耗RTC與電池供電的SRAM和事件檢測（具有電池供電的SRAM的和事件檢測功能的低功率實時時鐘） |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 373K |
| 代理商： | ISL1219 |
5
FN6314.1
August 14, 2006
SDA vs. SCL Timing
Symbol Table
t
F
SDA and SCL Fall Time
From 70% to 30% of V
DD.
20 +
0.1 x Cb
300
ns
7
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
7
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about
2~2.5k
. For Cb = 40pF, max is about
15~20k
1
k
7
NOTES:
2. IRQ and F
OUT
and EVDET Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. V
SUP
= V
DD
if in V
DD
Mode, V
SUP
= V
BAT
if in V
BAT
Mode.
7. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
8. A write to register 08h should only be done if V
DD
> V
BAT
, otherwise the device will be unable to communicate using I
2
C.
I
2
C Interface Specifications
Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 4)
MAX
UNITS
NOTES
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
ISL1219
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