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參數資料
| 型號： | ISL1219 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Power RTC with Battery Backed SRAM and Event Detection(具有電池供電的SRAM和事件檢測功能的低功率RTC) |
| 中文描述： | 低功耗RTC與電池供電的SRAM和事件檢測（具有電池供電的SRAM的和事件檢測功能的低功率實時時鐘） |
| 文件頁數： | 16/25頁 |
| 文件大小： | 373K |
| 代理商： | ISL1219 |
16
FN6314.1
August 14, 2006
For example, C
LOAD
(ATR = 00000) = 12.5pF,
C
LOAD
(ATR = 100000) = 4.5pF, and C
LOAD
(ATR = 011111)
= 20.25pF. The entire range for the series combination of
load capacitance goes from 4.5pF to 20.25pF in 0.25pF
steps. Note that these are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the V
DD
/V
BAT
operation, the ISL1219 provides the capability
to adjust the capacitance between V
DD
and V
BAT
when the
device switches between power sources.
DIGITAL TRIMMING REGISTER (DTR <2:0>)
The digital trimming bits DTR0, DTR1, and DTR2 adjust the
average number of counts per second and average the ppm
error to achieve better accuracy.
DTR2 is a sign bit. DTR2 = “0” means frequency
compensation is >0. DTR2 = “1” means frequency
compensation is <0.
DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -60ppm to +60ppm can be represented by
using these three bits (see Table 13).
Note that the DTR adjustment will affect the frequency of the
clock at F
OUT
, for all frequency selections except for
32.768kHz. DTR can be used in conjunction with ATR and
F
OUT
to accurately set the oscillator frequency (see the
Applications Section).
Alarm Registers
Addresses [0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
Single Event Mode
is enabled by setting the ALME bit to
“1”, the IM bit to “0”, and disabling the frequency output.
This mode permits a one-time match between the alarm
registers and the RTC registers. Once this match occurs,
the ALM bit is set to “1” and the IRQ output will be pulled
low and will remain low until the ALM bit is reset. This can
be done manually or by using the auto-reset feature.
Interrupt Mode
is enabled by setting the ALME bit to “1”,
the IM bit to “1”, and disabling the frequency output. The
IRQ output will now be pulsed each time an alarm occurs.
This means that once the interrupt mode alarm is set, it
will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for
hourly or daily hardware interrupts in microcontroller
applications such as security cameras or utility meter
reading.
To clear an alarm, the ALM bit in the status register must be
set to “0” with a write. Note that if the ARST bit is set to 1
(address 07h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
TABLE 12.
BMATR1
BMATR0
DELTA
CAPACITANCE
(C
BAT
TO C
VDD
)
0
0
0pF
0
1
-0.5pF (
≈
+2ppm)
1
0
+0.5pF (
≈
-2ppm)
1
1
+1pF (
≈
-4ppm)
TABLE 13. DIGITAL TRIMMING REGISTERS
DTR REGISTER
ESTIMATED
FREQUENCY PPM
DTR2
DTR1
DTR0
0
0
0
0 (default)
0
0
1
+20
0
1
0
+40
0
1
1
+60
1
0
0
0
1
0
1
-20
1
1
0
-40
1
1
1
-60
ISL1219
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