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參數(shù)資料
| 型號： | ISD5008EYI |
| 廠商： | Nuvoton Technology Corporation of America |
| 文件頁數(shù)： | 52/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VOICE REC/PLAY 4-8MIN 28-TSOP |
| 標(biāo)準(zhǔn)包裝： | 234 |
| 系列： | ISD5008 |
| 接口： | SPI/Microwire |
| 濾波器通頻帶： | 1.7 ~ 3.4kHz |
| 持續(xù)時間： | 4-8 分鐘 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.465"，11.8mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSOP |
| 配用： | ISD-ES511-ND - EVALUATION SYSTEM FOR ISD5100 ISD-ES501-ND - EVALUATION SYSTEM FOR ISD5008 |
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ISD5008
Publication Release Date: Oct 31 2008
- 7 -
Revision 1.2
5
PIN DESCRIPTION
PIN NAME
PDIP/SOIC
TSOP
FUNCTION
SCLK
1
8
Serial Clock
: The SCLK is the clock input to the ISD5008.
Generated
by
the
master
microcontroller,
the
SCLK
synchronizes data transfers in and out of the device through
the MISO and MOSI lines.
SS
2
9
Slave Select
: This input, when LOW, selects the device.
MOSI
3
10
Master Out Slave In
: MOSI is the serial data input to the
ISD5008 device. The master microcontroller places data to be
clocked into the ISD5008 device on the MOSI line one-half
cycle before the rising edge of SCLK. Data is clocked into the
device with LSB (Least Significant Bit) first.
MISO
4
11
Master In Slave Out
: MISO is the serial data output of the
ISD5008. Data is clocked out on the falling edge of SCLK. This
output goes into a high-impedance state when the device is not
selected. Data is clocked out of the device with LSB first.
VSSD / VSSA
5, 6 /
9, 15, 23
12, 13 /
2, 15,
22
Ground
: The ISD5008 utilizes separate analog and digital
ground busses. The analog ground (VSSA) pins should be tied
together as close to the package as possible and connected
through a low-impedance path to power supply ground. The
digital ground (VSSD) pin should be connected through a
separate low-impedance path to power supply ground. These
ground paths should be large enough to ensure that the
impedance between the VSSA pins and the VSSD pins is less
than 3 . The backside of the die is connected to VSSD through
the substrate resistance. In a chip-on-board design, the die
attach area must be connected to VSSD.
MIC+ / MIC-
8 / 10
16 / 17
Microphone +/–
: The microphone inputs transfer the voice
signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The AGC circuit
has a range of 45dB in order to deliver a nominal 694 mVp-p
into the storage array from a typical electret microphone output
of 2 to 20 mVp-p. The direct path to the ANA OUT MUX has a
gain of 6dB so a 208 mVp-p signal across the differential
microphone inputs would give 416 mVp-p across the ANA OUT
pins. The input impedance is typically 10 k.
ANAOUT+ /
ANAOUT-
11 / 12
18 / 19
Analog Outputs
: These differential outputs are designed to
match to the microphone input of the telephone chip set. It is
designed to drive a minimum of 5 k between the “+” and “–”
pins to a nominal voltage level of 700 mVp-p. Both pins have
DC bias of approximately 1.2 VDC. The AC signal is
superimposed upon this analog ground voltage. These pins
can be used single-ended, getting only half the voltage. Do
NOT
ground the unused pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISD5008P | 功能描述:IC VOICE REC/PLAY 4-8MIN 28-DIP RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5008PY | 功能描述:IC VOICE REC/PLAY 4-8MIN 28-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5008S | 功能描述:IC VOICE REC/PLAY 4-8MIN 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5008SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP VOICE RECORD PLAYBACK DEVICE 4-, 5-, 6-, AND 8- MINUTE DURATIONS |
| ISD5008SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Voice Record/Playback Device |
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