Publication Release Date: Oct 31 2008 - 33 - Revision 1.2 6.5.3 Sto and is not active in this mode. The path to be used i" />
參數(shù)資料
型號(hào)： ISD5008EYI
廠商： Nuvoton Technology Corporation of America
文件頁(yè)數(shù)： 27/54頁(yè)
文件大?。?/td> 0K
描述： IC VOICE REC/PLAY 4-8MIN 28-TSOP
標(biāo)準(zhǔn)包裝： 234
系列： ISD5008
接口： SPI/Microwire
濾波器通頻帶： 1.7 ~ 3.4kHz
持續(xù)時(shí)間： 4-8 分鐘
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.465"，11.8mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSOP
配用： ISD-ES511-ND - EVALUATION SYSTEM FOR ISD5100
ISD-ES501-ND - EVALUATION SYSTEM FOR ISD5008
ISD5008
Publication Release Date: Oct 31 2008
- 33 -
Revision 1.2
6.5.3
Sto
and is not active in this mode. The path to be used is microphone input to AGC amplifier, then through
FIL
STORAGE
power up the stage.
2.
Select the AGC amplifier through the INPUT SOURCE MUX—
Bit INS0 controls the state
to a ZERO to
UX (only) to the SUM1 SUMMING amplifier
—Bits S1M0
he SUM1 SUMMING amplifier. These are bits D7 and D8
he state where D7 is ZERO and D8 is
ONE to select the INPUT SOURCE MUX (only) path.
4.
Select the SUM1 SUMMING amplifier path through the FILTER MUX
—Bit FLS0 controls
MUX. This is bit D4 of CFG1 and it should be set to ZERO to
sample rate to be used during record and playback. These are bits D2 and D3 of
CFG1. To enable the 5.3 kHz sample rate, D2 should be set to ZERO and D3 set to ONE.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CF
Memo Record
The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
rage Array. A connected cellular telephone or cordless phone chip set may remain powered down
the INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the
TER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL
ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may
be powered down.
1.
Power up the AGC amplifier
—Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 of CFG1 and should be set to ZERO to
of the INPUT SOURCE MUX. This is bit D9 of CFG0 and should be set
select the AGC amplifier.
3.
Select the INPUT SOURCE M
and S1M1 control the state of t
respectively of CFG1 and they should be set to t
the state of the FILTER
select the SUM1 SUMMING amplifier path.
5.
Power up the LOW PASS FILTER
—Bit FLPD controls the power up state of the LOW
PASS FILTER stage. This is bit D1 of CFG1 and it should be set to ZERO to power up the
LOW PASS FILTER stage.
6.
Select the 5.3 kHz sample rate—
Bits FLD0 and FLD1 select the Low Pass filter setting
and
7.
Select the LOW PASS FILTER input (only) to the SUM2 SUMMING amplifier
—Bits S2M0
and S2M1 control the state of the SUM2 SUMMING amplifier. These bits are D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is
ONE to select the LOW PASS FILTER (only) path.
CFG0=0010 0100 0010 0001 (hex 2421).
G1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are powered up.
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ISD5008P 功能描述:IC VOICE REC/PLAY 4-8MIN 28-DIP RoHS:否 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
ISD5008PY 功能描述:IC VOICE REC/PLAY 4-8MIN 28-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
ISD5008S 功能描述:IC VOICE REC/PLAY 4-8MIN 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
ISD5008SD 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP VOICE RECORD PLAYBACK DEVICE 4-, 5-, 6-, AND 8- MINUTE DURATIONS
ISD5008SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Voice Record/Playback Device
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