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ISD5008
Publication Release Date: Oct 31 2008
- 45 -
Revision 1.2
measured at SP+/-
ANA OUT to SP+/- Cross
Talk
CRTANA
OUT/(SP+/-)
-65
dB
1kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
(12)
ANA OUT to AUX OUT
Cross Talk
CRTANA
OUT/AUX OUT
-65
dB
1kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
red at AUX OUT
measu
(12)
AUX OUT
(9)
AUX OUT – Maximum
VAUX OUT
1.0
Vpp
Output Swing
5 k Load
Minimum Load Impedence
R
5
k
L
Maximum
Load
Capacitance
CL
100
pF
AUX OUT
VBIAS
1.2
VDC
SINAD – ANA IN to AUX
OUT
SINAD
62.5
dB
0TLP
ANA
IN
input,
minimum gain, 5k load
(12)(13)
Idle Channel Noise – ANA
IN to AUX OUT
ICN(AUX
OUT)
-65
dB
Load = 5 k (12)(13)
AUX OUT to ANA OUT
Cross Talk
CRTAUX
OUT/ANA OUT
-65
dB
1 kHz 0TLP input to ANA
IN, with MIC +/- and AUX
IN AC coupled to VSSA,
and measured at SP+/-,
load = 5 k. Referenced
to
nominal
0TLP
@
output
VOLUME CONTROL
(9)
Output Gain
AOUT
-28 to 0
dB
8
Steps
of
4
dB,
referenced to output
Gain Accuracy
-0.5
0.5
dB
ANA IN = 1 kHz 0TLP,
6dB Gain setting
Notes:
1.
Typical values: TA = 25°C and Vcc = 3.0V.
2.
All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications
are 100 percent tested.
3.
Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).
4.
Differential input mode. Nominal differential input is 208 mVp-p. (0 dBm0)
5.
Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions). Sampling
frequency will be accurate within ±1% for 5.3kHz, and ±5% for 4.0, 6.4 and 8.0 kHz sampling rates at
room temperature.