參數(shù)資料
型號: IMIB9847BY
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48
封裝: SSOP-48
文件頁數(shù): 3/7頁
文件大?。?/td> 64K
代理商: IMIB9847BY
B9847
Document #: 38-07197 Rev. **
Page 3 of 7
Power Management
The individual output enable/disable control of the B9847 al-
lows the user to implement unique power management
schemes into the design. Outputs are three-stated when dis-
abled through the I2C interface as individual bits are set low in
Byte6 and Byte7 registers. The enabling and disabling of indi-
vidual outputs is done in such a manner as to eliminate the
possibility of partial “runt” clocks.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
3. Byte(0:5) are dummy bytes and are reserved. These
bytes should be sent as don’t care.
See our application note (AN0022) for more details on using
the I2C interface.
Figure 1. Differential Signal Using Direct Termination Resistor
Byte 6: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
0
-
Reserved
6
0
-
Reserved
5
0
-
Reserved
41
1
FBOUT
3
1
45, 44
DDR11T, DDR11C
2
1
43, 42
DDR10T, DDR10C
1
39, 38
DDR9T, DDR9C
0
1
34, 33
DDR8T, DDR8C
Byte 7: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
1
30, 29
DDR7T, DDR7C
6
1
28, 27
DDR6T, DDR6C
5
1
21, 22
DDR5T
DDR5C
4
1
19, 20
DDR4T/SDRAM6,
DDR4C/SDRAM7
3
1
15, 16
DDR3T/SDRAM4,
DDR3C/SDRAM5
2
1
10, 11
DDR2T/SDRAM2,
DDR2C/SDRAM3
1
6, 7
DDR1T/SDRAM0,
DDR1C/SDRAM1
0
1
4, 5
DDR0T
DDR0C
60 Ohm
Receiver
VCP
VTR
R
T = 120 Ohm
VDD
OUT
OUT#
VDD
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