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參數(shù)資料
| 型號： | IMIB9847BY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 64K |
| 代理商： | IMIB9847BY |
DDR Clock Distribution Buffer/Driver
B9847
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07197 Rev. **
Revised December 5. 2001
Features
Supports 266-MHz DDR SDRAM
Supports VIA Pro 266, PM266, and KT266 Chipsets
Operating Frequency: 60 MHz to 170 MHz
12 Differential or 6 Differential 8 single-ended outputs
Configurable Outputs: Drive 4 DDR DIIMS or 2 DDR
DIMMS and 2 SDRAM DIMMS
Spread Spectrum Compatible
Low Jitter (cycle-to-cycle): < 75 ps
Very Low Skew: < 100 ps
Power Management via I2C Interface and OE#/PD
2.5V and 3.3V Power Supplies
48-Pin SSOP
Description
The B9847 is a high-performance, low-skew, low-jitter buffer
designed to distribute differential clocks in high-speed applica-
tions. The B9847 generates twelve differential pair clock out-
puts or six differential and eight single-ended clock outputs
from one single-ended clock input. The B9847 outputs are
configurable to drive four DDR DIMMS or two DDR DIMMS
and two SDRAM DIMMS. In addition, the B9847 features a
feedback clock output, FBOUT. This output is for the chipset
or other B9847 devices and/or one of Cypress’s zero-delay
buffers. The B9847 is used with C9846 clock synthesizer for
the VIA Pro 266 chipset.
The I2C interface enables/disables differential pair outputs.
This feature allows flexibility in system power management.
The B9847 can also be shut down when PD# is asserted LOW,
which drives the outputs LOW.
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
DDR0T
DDR0C
Powedown
Logic
SDATA
SCLK
DDR1T/SDRAM0
DDR1CSDRAM1
DDR2T/SDRAM2
DDR2CSDRAM3
DDR3T/SDRAM4
DDR3CSDRAM5
DDR4T/SDRAM6
DDR4CSDRAM7
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
FBOUT
BUFIN
OE/PD#
SEL_DDR
and
Control
Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FBOUT
VDD3.3_2.5
VSS
DDR0T
DDR0C
DDR1T/SDRAM0
DDR1C/SDRAM1
VDD3.3_2.5
VSS
DDR2T/SDRAM2
DDR2C/SDRAM3
VDD3.3_2.5
BUFIN
VSS
DDR3T/SDRAM4
DDR3C/SDRAM5
VDD3.3_2.5
VSS
DDR4T/SDRAM6
DDR4C/SDRAM7
DDR5T
DDR5C
VDD3.3_2.5
SDATA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR
VDD2.5
VSS
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
VSS
DDR9T
DDR9C
VDD2.5
OE/PD#
VSS
DDR8T
DDR8C
VDD2.5
VSS
DDR7T
DDR7C
DDR6T
DDR6C
VSS
SCLK
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