參數(shù)資料
型號(hào)： IDT89HPES8T5ZHBC
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 4/31頁(yè)
文件大?。?/td> 0K
描述： IC PCI SW 8LANE 5PORT 324-BGA
標(biāo)準(zhǔn)包裝： 84
系列： PRECISE™
類型： PCI Express 開(kāi)關(guān) - Gen1
應(yīng)用： 服務(wù)器，儲(chǔ)存，通信，嵌入式，消費(fèi)品
安裝類型： 表面貼裝
封裝/外殼： 324-LBGA
供應(yīng)商設(shè)備封裝： 324-CABGA（19x19）
包裝： 托盤
其它名稱： 89HPES8T5ZHBC
12 of 31
March 27, 2008
IDT 89HPES8T5 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
AC Timing Characteristics
Parameter
Description
Min
Typical
Max
Unit
PEREFCLK
RefclkFREQ
Input reference clock frequency range
100
1251
1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
MHz
RefclkDC2
2. ClkIn must be AC coupled. Use 0.01 — 0.1 F ceramic capacitors.
Duty cycle of input clock
40
50
60
%
TR, TF
Rise/Fall time of input clocks
0.2*RCUI
RCUI3
3. RCUI (Reference Clock Unit Interval) refers to the reference clock period.
VSW
Differential input voltage swing4
4. AC coupling required.
0.6
1.6
V
Tjitter
Input clock jitter (cycle-to-cycle)
125
ps
RT
Termination Resistor
110
Ohms
Table 9 Input Clock Requirements
Parameter
Description
Min1
Typical1
Max1
Units
PCIe Transmit
UI
Unit Interval
399.88
400
400.12
ps
TTX-EYE
Minimum Tx Eye Width
0.7
.9
UI
TTX-EYE-MEDIAN-to-
MAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
0.15
UI
TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time
50
90
ps
TTX- IDLE-MIN
Minimum time in idle
50
UI
TTX-IDLE-SET-TO-
IDLE
Maximum time to transition to a valid Idle after sending
an Idle ordered set
20
UI
TTX-IDLE-TO-DIFF-
DATA
Maximum time to transition from valid idle to diff data
20
UI
TTX-SKEW
Transmitter data skew between any 2 lanes
500
1300
ps
PCIe Receive
UI
Unit Interval
399.88
400
400.12
ps
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
0.4
UI
TRX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation
0.3
UI
TRX-IDLE-DET-DIFF-
ENTER TIME
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
TRX-SKEW
Lane to lane input skew
20
ns
Table 10 PCIe AC Timing Characteristics
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