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參數(shù)資料
| 型號： | IDT89HPES8T5ZHBC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 27/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI SW 8LANE 5PORT 324-BGA |
| 標準包裝： | 84 |
| 系列： | PRECISE™ |
| 類型： | PCI Express 開關 - Gen1 |
| 應用： | 服務器，儲存，通信，嵌入式，消費品 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-LBGA |
| 供應商設備封裝： | 324-CABGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 89HPES8T5ZHBC |
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March 27, 2008
IDT 89HPES8T5 Data Sheet
PE4RP[0]
PE4RN[0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PE4TP[0]
PE4TN[0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
PE5RP[0]
PE5RN[0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
PE5TP[0]
PE5TN[0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 5.
PEREFCLKP[2:1]
PEREFCLKN[2:1]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1]
I
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
Signal
Type
Name/Description
Table 2 PCI Express Interface Pins (Part 2 of 2)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT89HPES8T5ZHBCG | 功能描述:IC PCI SW 8LANE 5PORT 324-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89HT0808PYAAB | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE RETIMER 8CH 100CABGA |
| IDT89HT0808PYAABG | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE RETIMER 8CH 100CABGA |
| IDT89HT0808PYAABG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE RETIMER 8CH 100CABGA |
| IDT89HT0808PYAABGI | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE RETIMER 8CH 100CABGA |
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