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| 型號： | IDT88P8342BHGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 73/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8342BHGI |
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
DIP_2 The DIP_2 field is used to read the number of DIP-2 errors seen on
the SPI-4 egress status interface. The DIP_2 field saturates at the value
0xFFFF, and is automatically cleared after reading to re-start DIP-2 error
counteraccumulation.
9.4.9 Common module block base 0x0800 registers
SPI-4 ingress bit alignment window register
(Block_base 0x0800 + Register_offset 0x00)
TheSPI-4ingressbitalignmentwindowregisterisaddressedfromBlock_base
0x0800+Register_offset0x00.TheSPI-4ingressbitalignmentwindowregister
has read and write access. The SPI-4 ingress bit alignment window register is
used in manual bit alignment procedures and it is recommended to leave the
W field at its initial value.
W
TheWfieldisusedtodefinethewidthoftheSPI-4ingressbitalignment
observation window by setting the time between bit alignment operations. .
SPI-4 ingress lane measure register (Block_base
0x0800 + Register_offset 0x01)
The SPI-4 ingress lane measure register is addressed from Block_base
0x0800 + Register_offset 0x01. The SPI-4 ingress lane measure register has
read and write access. SPI-4 ingress lane measure register is used in manual
bitalignmentproceduresanditisrecommendedtoleavetheSPI-4ingresslane
measure register at its initial value.
LANE TheLANEfieldisusedtomanuallycontrolthemeasurementofSPI-
4 ingress data lane alignment. The LANE field is intended for diagnostics only
and is not needed in normal operation.
0=DATA0 lane selected for measurement
x=DATAx lane selected for measurement
15=DATA15 lane selected for measurement
16=CTL selected for measurement
17=Egress status 0 selected for measurement
18=Egress status 1 selected for measurement
19=Chip test feature not available for diagnostics
MEASURE_BUSY
The MEASURE_BUSY field is used to observe
when the LANE process is busy for manual lane assignment procedures. The
MEASURE_BUSY field is intended for diagnostics only and is not needed for
normal operation.
0=Normal operation
1=Lane process is busy
SPI-4 ingress bit alignment counter register
(Block_base 0x0800 + Register_offset 0x02 – 0x0B)
The SPI-4 ingress manual alignment phase/result registers at Block_base
0x0800havereadandwriteaccess.ASPI-4ingressmanualalignmentphase/
result register is used to manually align the phase of the data lane, control lane,
statuslanes,andatestlanecorrespondingtoitsregisterinturnandisintended
for diagnostics only and is not needed in normal operation. If the FORCE field
of Table 99, SPI-4 ingress bit alignment control register (register_offset 0x11)
is set to a logic one, manual phase alignment is enabled. If the FORCE field is
settoalogiczero,normalautomaticphasealignmentisenabled,andtheresult
can be viewed here. There are five center taps to choose from, plus two guard
taps on either side of the center, per data bit sampled. The oldest data sample
is at tap 8 ("right"), while the newest data sample is at tap 0 ("left"). Taps 0 and
1 are the left margin taps for tracking purposes, while taps 7 and 8 are the right
margin taps. A tap between 2 to 7 is initially selected in automatic mode. See
Figure 7-Data sampling diagram. Register 0x0C is used for lane DATA0.
PHASE_ASSIGN [3:0]
Used for selecting the bit phase corresponding to the rising clock edge of
I_DCLK. The four bits number the phases from 0 to 8, relative to the positively-
clockedbit.
PHASE_ASSIGN [7:4]
Used for selecting the bit phase corresponding to the falling clock edge of
I_DCLK.Thefourbitsnumberthephasesfrom0to8,relativetothenegatively-
clockedbit.
SPI-4 egress data lane timing register (Block_base
0x0800 + Register_offset 0x2A)
TABLE 110 - SPI-4 INGRESS BIT ALIGNMENT
WINDOW REGISTER (REGISTER_OFFSET 0x00)
Field
Bits
Length
Initial Value
LANE
4:0
5
0
Reserved
7:5
3
0
MEASURE_BUSY
8
1
0
TABLE 111 - SPI-4 INGRESS LANE MEASURE
REGISTER (REGISTER_OFFSET 0x01)
Field
Bits
Length
Initial Value
W
15:0
16
0xFFFF
TABLE 112 - SPI-4 INGRESS BIT ALIGNMENT
COUNTER REGISTER (0x02 to 0x0B)
Field
Bits
Length
Initial Value
C[n]
9:0
10
0
TABLE 113 - SPI-4 INGRESS MANUAL ALIGNMENT
PHASE/RESULT REGISTER (0x0C to 0x1F)
Field
Bits
Length
Initial Value
DTC0[1:0]
1:0
2
0
DTC1[1:0]
3:2
2
0
…..
2
0
DTC15[1:0]
31:30
2
0
TABLE 114 - SPI-4 EGRESS DATA LANE TIMING
REGISTER (REGISTER_OFFSET 0x2A)
The SPI-4 egress data lane timing register at Block_base 0x0800 +
Register_offset 0x2A has read and write access. The SPI-4 egress data lane
timingregisterisusedtomanuallyalignthephaseofdatalanenbyaddingfrom
0.1 clock cycle to 0.3 clock cycles of delay.
Field
Bits
Length
Initial Value
PHASE_ASSIGN
7:0
8
0
TheSPI-4ingressbitalignmentcounterregistersatBlock_base0x0800are
read-onlyandcontainsthevaluesofthebitalignmentcountersusedformanual
lane alignment . The registers are intended for diagnostics only and are not
needed in normal operation.
SPI-4 ingress manual alignment phase/result
register (Block_base 0x0800 + Register_offset
0x0C – 0x1F)
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| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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