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參數(shù)資料
型號： IDT88P8342BHGI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 13/98頁
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8342BHGI
20
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Normal status information when in the IN_SYNCH state
The normal status information is generated based on ingress buffer full
information and PFP buffer segment fill level.
ForinformationonDIP-2generationandtrainingpatternrefertotheOIFSPI-
4 document [Glossary].
DIP-2 error insertion
AnumberofconsecutiveDIP-2errorscanbegenerated.The I_DIP_E_NUM
field in Table 97, SPI-4 ingress diagnostics register (register_offset 0x0F)
specifies the number of errors to be generated. A logic one written to
I_ERROR_INSwillactivatetheI_DIP_E_NUMfieldandtriggererrorinsertion.
The I_ERROR_INS field self clears when the number of errors have been
generated.
LVTTL and LVDS status interface selection
TheLVDS_STApinselectswhichFIFOstatusinterfaceisbeingusedforSPI-
4. HIGH = LVDS status interface, LOW = LVTTL status interface.
3.2.2 SPI-4 egress
The SPI-4 egress includes
Statuschannelsynchronization
Statusupdating
Datatransfer
Periodictraining
PFPinterface
SPI-4 egress configurable parameters
All parameters as listed in the 0IF SPI-4 document [see Glossary]
CALENDAR_LEN: 4 to 1,024 in increments of 4
CALENDAR_M: 1 to 256 in increments of 1
MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16
MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16
Alpha: 1 to 256 in increments of 1
DATA_MAX_T: 1 to 4,294,967,040 in increments of 1
FIFO_MAX_T: 1 to 16,777,215 in increments of 1
Calendar and shadow calendar
- 256 entries
- E_CSW_EN field in Table 104, SPI-4 egress configuration register_0
(register_offset 0x00) bit for manual reconfiguration swap
Multiple burst enable
- Allows more than one burst to be sent to an LP. Feature included to relieve
systems with long latency between updates.
SPI-4 egress LID to LP map
- 256 entries, one per SPI-4 LP
- Enable bit
Ingress
egress
Out of synch, send status training
Out of synch, send data training
In synch, send status frame
Out of synch, send data training
In synch, send status frame
In synch, send data/idle
3.2.3 SPI-4 startup handshake
Ingress
Egress
Out of synch, send status training
In synch, send data/idle
Out of synch, send status training
Out of synch, send data training
In synch, send status frame
Out of synch, send data training
In synch, send status frame
In synch, send data/idle
TABLE 11 – INGRESS OUT OF SYNCH, EGRESS IN SYNCH
TABLE 10 – BOTH ATTACHED DEVICES START FROM RESET STATUS
Ingress
Egress
In synch, send status frame
Out of synch, send data training
Out of synch, send status training
Out of synch, send data training
In synch, send status frame
Out of synch, send data training
In synch, send status frame
In synch, send data/idle
TABLE 12 – INGRESS IN SYNCH, EGRESS OUT OF SYNCH
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IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
IDT88P8344BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT89H10T4BG2ZBBC 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
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