參數(shù)資料
型號(hào): IDT88P8341BHGI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 28/96頁(yè)
文件大小: 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88P8341BHGI
34
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
4.3.2 Microprocessor insert to SPI-3 egress
datapath
The diagram below shows the datapath through the device from the
microprocessor data insert interface to a SPI-3 egress port.
The following is a description of the path taken by a fragment of data through
the device.
Data and control information are written to the insert buffer through the
microprocessorinterface.Thedataavailablebitisset.Dataisstoredalongwith
itsLPaddress,LID(includingSPI-3choice),errorinformation,SOP,andEOP.
Data is stored in LID-allocated buffer segments. The Table 80, SPI-3 egress
port descriptor table (64 entries) is consulted and the PFP decides to move the
data to the SPI-3 egress port. The SPI-3 packet fragment processor chooses
the next LP. The choice of LP is dependent on the status of the LP and the
availabilityofacompletefragment.DataismovedtoaSPI-3egressbufferalong
with its LP address. SPI-3 LP address, error information, SOP, and EOP.
Data is transmitted in packet fragments over the selected SPI-3 egress
interface.
Figure 24. Microprocessor interface to SPI-3 egress detailed datapath diagram
Figure 23. Microprocessor data insert buffer
6372 drw22
flags
length
data[1]
data[2]
data[255]
lid
data[0]
SOP
EA
ED
PAR
EOP
not used
EA
ED
PAR
data parity error
address parity error
packet error
70
inser
tsequence
t
t+1
t+258
e
xtr
act
sequence
t
t+1
t+258
JTAG
uproc
LID Counters Memory
SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
Interface
Bloc
k
Chip Counters Memory
Interface
Bloc
k
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6372 drw24
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