參數(shù)資料
型號(hào)： IDT82P20516DBFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 45/115頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝： 84
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 16
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.89W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-LFBGA
供應(yīng)商設(shè)備封裝： 484-CABGA（19x19）
包裝： 托盤
包括： AIS 警報(bào)檢測(cè)器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測(cè)器，遠(yuǎn)程檢測(cè)器和發(fā)生器
IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Functional Description
35
December 17, 2009
3.5.4
ALARM INDICATION SIGNAL (AIS) DETECTION AND GEN-
ERATION
3.5.4.1 Alarm Indication Signal (AIS) Detection
AIS is monitored in both the receive path and the transmit path.
When the mark density in the received data or in the data input from
the transmit system side meets certain criteria, AIS is declared or
cleared. In E1 mode, the criteria are in compliance with ITU G.775 or
ETSI 300233, as selected by the LAC bit (b7, LOS,...). Refer to Table-13
for details.
When AIS is detected in the receive path, the LAIS_S bit (b6,
STAT1,...) will be set. A transition from ‘0’ to ‘1’ on the LAIS_S bit (b6,
STAT1,...) or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LAIS_S
bit (b6, STAT1,...) will set the LAIS_IS bit (b6, INTS1,...) to ‘1’, as
selected by the AIS_IES bit (b6, INTES,...). When the LAIS_IS bit (b6,
INTS1,...) is ‘1’, an interrupt will be reported by INT if not masked by the
LAIS_IM bit (b6, INTM1,...).
When AIS is detected in the transmit path, the SAIS_S bit (b7,
STAT1,...) will be set. A transition from ‘0’ to ‘1’ on the SAIS_S bit (b7,
STAT1,...) or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the
SAIS_S bit (b7, STAT1,...) will set the SAIS_IS bit (b7, INTS1,...) to ‘1’,
as selected by the AIS_IES bit (b6, INTES,...). When the SAIS_IS bit
(b7, INTS1,...) is ‘1’, an interrupt will be reported by INT if not masked by
the SAIS_IM bit (b7, INTM1,...).
AIS may be counted by an internal Error Counte. Refer to
3.5.4.2 (Alarm Indication Signal) AIS Generation
AIS can be generated automatically in the receive path and the
transmit path.
In the receive path, when the ASAIS_LLOS bit (b2, AISG,...) is set,
AIS will be generated automatically once LLOS is detected. When the
ASAIS_SLOS bit (b3, AISG,...) is set, AIS will be generated automati-
cally once SLOS is detected. When AIS is generated, RDPn/RDNn
output all ‘1’s. RCLKn (if available) outputs XCLK.
In the transmit path, when the ALAIS_LLOS bit (b0, AISG,...) is set,
AIS will be generated automatically once LLOS is detected. When the
ALAIS_SLOS bit (b1, AISG,...) is set, AIS will be generated automati-
cally once SLOS is detected. When AIS is generated, TTIPn/TRINGn
output all ‘1’s.
In the transmit path, the AIS transmission is controled by the TXAIS
bit (b4, AISG,...). When the TXAIS bit (b4, AISG,...) is set to ‘1’, all ‘1’s
pattern is transmitted at TTIPn/TRINGn.
AIS generation uses XCLK1 as reference clock.
If pattern (including PRBS, ARB and IB) is generated in the same
direction, the priority of pattern generation is higher. The generated
pattern will overwrite automatic AIS. Refer to Section 3.5.5.1 Pattern
Generation for the output data and clock.
Table-13 AIS Criteria
ITU G.775 for E1 (LAC = 0)
ETSI 300233 for E1 (LAC = 1)
AIS Declaring
Less than 3 zeros are received in each of two consecutive 512-bit data
streams.
Less than 3 zeros are received in a 512-bit data
stream.
AIS Clearing
3 or more zeros are received in each of two consecutive 512-bit data
streams.
3 or more zeros are received in a 512-bit data stream.
1. XCLK is derived from MCLK. It is 2.048 MHz in E1 mode.
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