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參數(shù)資料
| 型號： | ICSSSTUAF32869AHLF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 14位可配置注冊緩沖內(nèi)存 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 426K |
| 代理商： | ICSSSTUAF32869AHLF |
ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
7
ICSSSTUAF32869A
7095/13
Terminal Functions
Signal
Group
Ungated
Inputs
Chip Select
Gated Inputs
Terminal
Name
Type
Description
DCKE, DODT
SSTL_18
DRAM function pins not associated with Chip Select
D1...D14
1
1
This range does not include D1, D4, and D7, and their corresponding outputs.
SSTL_18
DRAM inputs, re-driven only when Chip Select is LOW
Chip Select
Inputs
DCS, CSR
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
LOW when a valid address/command is present.
Re-Driven
Outputs
Q1A...Q14A
1
,
Q1B...Q14B
1
,
QCSnA, B
QCKEnA, B
QODTnA, B
SSTL_18
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock
Parity Input
PARIN
SSTL_18
Input parity is received on pin PARIN, and should maintain odd
parity across the D1:D14 inputs, at the rising edge of the clock,
one cycle after Chip Select is LOW.
Partial Parity Output. Indicates parity out of D1-D14.
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by in
total two clock cycles for compatibility with final parity out timing
on the industry-standard DDR2 register with parity (in JEDEC
definition).
When LOW, the register is configured as Register 1. When
HIGH, the register is configured as Register 2.
Differential master clock input pair to the register. The register
operation is triggered by a rising edge on the positive clock
input (CLK).
Asynchronous Reset Input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET also
resets the PTYERR signal.
Input reference voltage for SSTL_18 inputs. Two pins
(internally tied together) are used for increased
Inputsreliability.
Power Supply Voltage
Ground
Parity Output
PPO
SSTL_18
Parity Error
Output
PTYERR
Open Drain
Configuration
Inputs
C1
SSTL_18
Clock Inputs
CLK, CLK
SSTL_18
Miscellaneous
Inputs
RESET
SSTL_18
Input
V
REF
0.9V nominal
V
DD
GND
Power Input
Ground Input
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