參數(shù)資料
型號(hào)： ICSSSTUAF32869AHLF
廠商： Integrated Device Technology, Inc.
英文描述： 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
中文描述： 14位可配置注冊(cè)緩沖內(nèi)存
文件頁(yè)數(shù)： 12/21頁(yè)
文件大?。?/td> 426K
代理商： ICSSSTUAF32869AHLF
ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
12
ICSSSTUAF32869A
7095/13
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol
f
CLOCK
t
W
t
ACT1
t
INACT2
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
DCS before CLK
↑
, CLK
↓
, CSR HIGH; CSR before
CLK
↑
, CLK
↓
, DCS HIGH
DCS before CLK
↑
, CLK
↓
, CSR LOW
DODT, DOCKE, and data before CLK
↑
, CLK
↓
PAR_IN before CLK
↑
, CLK
↓
DCS, DODT, DCKE, and data after CLK
↑
, CLK
↓
PAR_IN after CLK
↑
, CLK
↓
V
DD
= 1.8V ± 0.1V
Min.
Units
MHz
ns
ns
ns
Max.
410
1
1
minimum time of t
ACT
(max) after RESET is taken HIGH.
2
V
REF
, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
time of t
INACT
(max) after RESET is taken LOW.
V
REF
must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
10
15
t
SU
Setup
Time
0.7
ns
0.5
0.5
0.5
0.5
0.5
t
H
Hold
Time
ns
Symbol
f
MAX
t
PDM
t
PDMSS
t
LH
t
HL
t
PD
t
PHL
t
PLH
Parameter
Max Input Clock Frequency
Propagation Delay, single-bit switching, CLK
↑
/ CLK
↓
to Qn
Propagation Delay, simultaneous switching, CLK
↑
/ CLK
↓
to Qn
LOW to HIGH Propagation Delay, CLK
↑
/ CLK
↓
to PTYERR
HIGH to LOW Propagation Delay, CLK
↑
/ CLK
↓
to PTYERR
Propagation Delay from CLK
↑
/ CLK
↓
to PPO
HIGH to LOW Propagation Delay, RESET
↓
to Qn
↓
LOW to HIGH Propagation Delay, RESET
↓
to PTYERR
↑
V
DD
= 1.8V ± 0.1V
Min.
340
1.1
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Max.
1.9
2
3
2.4
1.6
3
3
0.9
0.4
0.3
相關(guān)PDF資料
PDF描述
ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868AHLF 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUB32864A 25-Bit Configurable Registered Buffer for DDR2
ICSSSTUB32864Az(LF)T 25-Bit Configurable Registered Buffer for DDR2
ICT49FCT3805APY 3.3V CMOS BUFFER/CLOCK DRIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICSSSTUAH32865A 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32865AHLFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868A 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868AHLF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUB32864A 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-Bit Configurable Registered Buffer for DDR2
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*