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| 型號(hào)： | ICSSSTUAF32869AHLF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 14位可配置注冊(cè)緩沖內(nèi)存 |
| 文件頁(yè)數(shù)： | 16/21頁(yè) |
| 文件大?。?/td> | 426K |
| 代理商： | ICSSSTUAF32869AHLF |
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ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
16
ICSSSTUAF32869A
7095/13
Test Circuits and Waveforms (V
DD
= 1.8V ± 0.1V)
Simulation Load Circuit
Voltage and Current Waveforms Inputs Active and Inactive
Times
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
Production-Test Load Circuit
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
NOTES:
1. C
L
includes probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DD
or GND, and
Io = 0mA
3. All input pulses are supplied by generators having the following
characteristics: PRR
≤
10MHz, Zo = 50
Ω
, input slew rate = 1 V/ns
±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per
measurement.
5. V
TT
= V
REF
= V
DD
/2
6. V
IH
= V
REF
+ 250mV (AC voltage levels) for differential inputs.
V
IH
= V
DD
for LVCMOS input.
7. V
IL
= V
REF
- 250mV (AC voltage levels) for differential inputs.
V
IL
= GND for LVCMOS input.
8. V
ID
= 600mV.
9. t
PLH
and t
PHL
are the same as t
PDM
.
C
L
= 30 pF
R
L
= 1K
Ω
DUT
Out
R
L =
100
Ω
CLK Inputs
T
L
= 50
Ω
T
L
= 350ps, 50
Ω
Test Point
CLK
CLK
V
DD
R
L
= 1K
Ω
Test Point
Test Point
V
DD
0V
V
DD
/2
LVCMOS
RESET
Input
I
DD
V
DD
/2
t
INACT
t
ACT
10%
90%
V
ICR
V
ID
V
ICR
Input
t
W
V
REF
V
IH
V
IL
V
REF
Input
V
ICR
V
ID
t
SU
t
H
CLK
CLK
Z
O
= 50
Ω
Test
Point
R
L
= 50
Ω
DUT
Out
CLK Inputs
CLK
V
DD
/2
CLK
Z
O
= 50
Ω
Z
O
= 50
Ω
Test
Point
Test
Point
CLK
V
ICR
V
ID
t
PLH
t
PHL
Output
V
OH
V
OL
V
ICR
V
TT
V
TT
CLK
V
OH
V
OL
V
IH
V
IL
t
RPHL
V
DD
/2
V
TT
LVCMOS
RESET
Input
Output
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