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參數(shù)資料
| 型號： | ICSSSTUAF32869AHLF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 14位可配置注冊緩沖內(nèi)存 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 426K |
| 代理商： | ICSSSTUAF32869AHLF |
ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
11
ICSSSTUAF32869A
7095/13
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 0°C to +70°C, V
DDQ
/V
DD
= 1.8V ± 0.1V.
Symbol
Parameter
V
IK
I
I
= -18mA
V
DDQ
= 1.7V, I
OH
= -100
μ
A
V
DDQ
= 1.7V, I
OH
= -12mA
V
DDQ
= 1.7V, I
OL
= 100
μ
A
V
DDQ
= 1.7V, I
OL
= 12mA
PTYERR Output
Low Voltage
I
IL
All Inputs
V
I
= V
DD
or GND
Static Standby
I
O
= 0, V
DD
= 1.9V, RESET = GND
I
O
= 0, V
DD
= 1.9V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK = CLK = V
IH
(
AC
)
or V
IL
(
AC
)
I
O
= 0, V
DD
= 1.9V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK = V
IH
(
AC
), CLK =
V
IL
(
AC
)
Dynamic
Operating (clock
only)
switching 50% duty cycle
I
O
= 0, V
DD
= 1.8V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK and CLK
switching 50% duty cycle. One data
input switching at half clock frequency,
50% duty cycle.
Dn, PARIN, DSCn
inputs
CLK and CLK
inputs
RESET
V
I
= V
DD
or GND
Test Conditions
Min.
Typ.
Max.
-1.2
Units
V
V
OH
V
DDQ
-0.2
1.2
V
V
OL
0.2
0.5
0.5
V
V
ERROL
I
ERROL
= 25mA; V
DD
= 1.7V
V
-5
+5
200
μ
A
μ
A
I
DD
Static Operating
10
mA
120
I
DDD
I
O
= 0, V
DD
= 1.8V, RESET = V
DD
, V
I
=
V
IH
(
AC
) or V
IL
(
AC
), CLK and CLK
247
μ
A/Clock
MHz
Dynamic
Operating (per
each data input)
52
μ
A/Clock
MHz/
Data
C
IN
V
I
= V
REF
± 250mV
2
3
pF
V
ICR
= 0.9V, V
IPP
= 600mV
3.5
4.5
5
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