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參數(shù)資料
| 型號： | ICSSSTUA32S869B |
| 英文描述： | 14-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 14位可配置的注冊緩沖DDR2內存 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ICSSSTUA32S869B |
5
ICSSSTUA32S869B
Advance Information
1173—10/28/05
Terminal Functions
NOTE 1 Inputs D1, D4 and D7 and their corresponding outputs Qn are not included in this range.
Signal Group
Signal Name
Type
Description
Ungated inputs DCKE, DODT
SSTL_18
DRAM function pins not associated with Chip Select.
Chip Select
gated inputs
D1 ... D14
(1)
SSTL_18
DRAM inputs, re-driven only when Chip Select is LOW.
Chip Select
inputs
DC
S#, CSR#
SSTL_18
DRAM Chip Select signals. This pins initiate DRAM address/
command decodes, and as such at least one will be low when
a valid address/command is present.
Re-driven
outputs
Q1A...Q14A,
Q1B ... Q14B,
QCSA#, QCSB#
QCKEA,QCKEB
QODTA,QODTB
SSTL_18
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
Parity input
PARIN1
SSTL_18
SSTL_18
Inout parity is received on pin PARIN1 and should maintain
parity across the D1...D14
(1)
inputs, at the rising edge of the
clock, one cycle after Chip Select is LOW.
Parity output
PPO1
Partial Parity Output. Indicates parity out of D1-D14
(1)
Parity error
output
PTYERR1#
Open drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR1# will be active for two clock cycles, and delayed
by in total 2 clock cycles for compatibility with final parity
out timing on the industry-standard DDR2 register with
parity (in JEDEC definition).
Configuration
Inputs
C1
1.8V
LVCMOS
When Low, register is configured as Register 1. When High,
register is confugured as Register 2.
Clock inputs
CK, CK#
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
Miscellaneous
inputs
RESET#
1.8 V
LVCMOS
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET#
also resets the PTYERR# signal.
VREF
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
VDD
Power Input
Power supply voltage
GND
Ground Input
Ground
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