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參數(shù)資料
| 型號： | ICSSSTUA32S869B |
| 英文描述： | 14-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 14位可配置的注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ICSSSTUA32S869B |
14
ICSSSTUA32S869B
Advance Information
1173—10/28/05
Output slew rate measurement information (V
DD
= 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR
10 MHz;
Z
o
= 50
; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) C
L
includes probe and jig capacitance.
Figure 12 — Load circuit, HIGH-to-LOW slew measurement
Figure 13 — Voltage waveforms, HIGH-to-LOW slew rate measurement
(1) C
L
includes probe and jig capacitance.
Figure 14 — Load circuit, LOW-to-HIGH slew measurement
Figure 15 — Voltage waveforms, LOW-to-HIGH slew rate measurement
CL = 10 pF
SEE NOTE (1)
VDD
OUT
DUT
TEST POINT
RL = 50
002aaa377
VOH
VOL
OUTPUT
80%
20%
dv_f
dt_f
002aaa378
CL = 10 pF
SEE NOTE (1)
OUT
DUT
TEST POINT
RL = 50
002aaa37
9
VOH
VOL
80%
20%
dv_r
dt_r
OUTPUT
002aaa380
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