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參數(shù)資料
| 型號(hào)： | ICS950401 |
| 英文描述： | AMD - K8TM System Clock Chip |
| 中文描述： | AMD公司- K8TM系統(tǒng)時(shí)鐘芯片 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | ICS950401 |
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6
ICS950401
0499C—11/01/04
load of the input frequency select pin conditions.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
W
P
7
t
B
7
1
6
t
B
8
1
5
t
B
2
2
1
4
t
B
1
2
1
3
t
B
8
1
1
2
t
B
7
1
1
1
t
B
4
1
1
0
t
B
3
1
1
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
W
P
7
t
B
6
3
,
3
6
t
B
0
4
,
4
5
t
B
5
4
4
t
B
8
4
3
t
B
1
2
t
B
8
2
1
t
B
1
3
0
t
B
1
1
D
N
O
I
T
)
N
P
I
(
R
1
0
C
_
_
S
C
C
E
/
K
/
K
D
L
L
1
1
1
1
1
1
1
1
C
C
2
1
0
8
4
H
M
C
I
C
U
U
F
F
F
_
P
P
E
E
E
4
8
C
C
R
R
R
2
4
P
z
H
M
z
K
L
2
_
6
6
3
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
Byte 4: Read-Back Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
7
t
B
3
2
6
t
B
4
4
5
t
B
8
2
4
t
B
6
3
t
B
5
4
2
t
B
8
4
1
t
B
1
0
t
B
-
Note: Can be optionally used as PCI33_F enable
control.
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
0
0
1
0
0
0
0
0
P
N
O
I
T
P
I
R
C
S
E
D
t
t
t
t
t
t
t
t
D
I
R
O
D
N
E
V
D
I
N
O
I
V
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
0
0
0
0
0
1
1
1
P
N
O
I
T
P
I
R
C
S
E
)
N
)
N
)
N
)
N
)
N
)
N
)
N
)
N
D
(
(
(
(
(
(
(
(
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
e
B
e
B
e
B
e
B
e
B
e
B
e
B
e
B
Byte 6: Byte Count Register
(1= enable, 0 = disable)
Note:
Writing to this register will configure byte count
and how many bytes will be read back. Default
state is 07H = 7 bytes.
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
-
2
2
1
2
8
1
7
1
4
1
3
1
I
P
D
W
0
0
0
0
0
0
0
0
P
N
O
I
T
P
I
R
C
S
E
D
)
e
)
e
5
K
4
K
L
K
L
C
K
L
C
I
L
C
I
C
L
C
I
C
P
t
t
t
t
t
t
t
t
v
R
v
R
(
I
C
P
I
C
P
I
C
P
C
P
P
(
)
N
)
N
(
)
N
(
)
N
(
)
N
(
)
N
(
(
L
C
C
3
2
1
0
K
K
D
N
O
I
T
P
I
R
1
_
0
_
C
6
6
S
E
6
3
6
3
5
4
K
3
K
2
K
1
K
0
K
D
K
K
K
L
L
L
L
L
L
L
L
C
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
C
C
C
C
C
C
C
C
P
P
P
P
P
P
P
P
D
W
1
1
1
1
1
1
1
0
P
N
O
I
T
P
I
R
C
)
N
S
(
E
F
D
_
K
D
A
E
S
8
6
3
C
p
2
S
F
p
1
S
F
p
0
S
F
v
R
(
L
C
E
4
I
R
_
C
P
4
P
S
2
P
L
S
6
u
w
o
u
w
o
u
w
o
)
e
#
c
p
c
p
c
p
L
E
e
e
e
n
n
n
d
d
d
e
e
e
h
h
h
Note:
This bit can be optional to disable the CPUCLKT/
C1 clock pair; CPUCLKT=L, CPUCLKC=H.
Note:
The above individual free running enable/disable
controls are intended to allow individual clock
outputs to be made free running. A clock output
that has it's free running bit enabled will not be
turned off with the assertion of either PCI_STOP#.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS950402 | AMD - K8 System Clock Chip |
| ICS950402YFLF-T | AMD - K8 System Clock Chip |
| ICS950402YGLF-T | AMD - K8 System Clock Chip |
| ICS950403 | AMD - K8⑩ System Clock Chip |
| ICS950403 | AMD - K8⑩ System Clock Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS950402 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
| ICS950402YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
| ICS950402YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
| ICS950403 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8? System Clock Chip |
| ICS950405 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
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