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參數(shù)資料
| 型號(hào)： | ICS950401 |
| 英文描述： | AMD - K8TM System Clock Chip |
| 中文描述： | AMD公司- K8TM系統(tǒng)時(shí)鐘芯片 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 108K |
| 代理商： | ICS950401 |
2
ICS950401
0499C—11/01/04
Pin Descriptions
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PIN
NAME
PIN
TYPE
I/O
PWR
IN
OUT
PWR
IN
IN
IN
PWR
PWR
IN
NC
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
I/O
*FS0/REF0
VDDREF
X1
X2
GND
*PCI33/HT66SEL#
PCICLK33/HT66_0
PCICLK33/HT66_1
VDDPCI
GND
PCICLK33/HT66_2
NC
PCICLK0
PCICLK1
GND
VDDPCI
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK_F
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz,
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
No Connect
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
Input select pin, Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ground pin.
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
Power supply, nominal 3.3V
Ground pin.
48MHz clock output.
3.3V power for the PLL core.
Ground pin for the PLL core.
Ground pin.
Power supply, nominal 3.3V
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
True clock of differential CPU outputs. Push-pull requires external termination.
Supply for CPU clocks, 3.3V nominal
Ground pin.
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
True clock of differential CPU outputs. Push-pull requires external termination.
Ground pin for the PLL core.
3.3V power for the PLL core.
Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable
spread spectrum functionality.
14.318 MHz reference clock / Frequency select latch input pin.
Ref, XTAL power supply, nominal 3.3V
Ground pin.
14.318 MHz reference clock / Frequency select latch input pin.
24
*PCI_STOP#
I/O
25
26
27
SCLK
SDATA
GND
IN
I/O
PWR
28
24_48MHz/Sel24_48#*
I/O
29
30
31
32
33
34
35
VDD
GND
48MHz
VDDA
GNDA
GND
VDD
PWR
PWR
OUT
PWR
PWR
PWR
PWR
36
CPUCLKC1
OUT
37
38
39
CPUCLKT1
VDDCPU
GND
OUT
PWR
PWR
40
CPUCLKC0
OUT
41
42
43
CPUCLKT0
GNDA
VDDA
OUT
PWR
PWR
44
SPREAD*
IN
45
46
47
48
REF2/FS2*
VDDREF
GND
REF1/FS1*
I/O
PWR
PWR
I/O
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS950402 | AMD - K8 System Clock Chip |
| ICS950402YFLF-T | AMD - K8 System Clock Chip |
| ICS950402YGLF-T | AMD - K8 System Clock Chip |
| ICS950403 | AMD - K8⑩ System Clock Chip |
| ICS950403 | AMD - K8⑩ System Clock Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS950402 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
| ICS950402YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
| ICS950402YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
| ICS950403 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8? System Clock Chip |
| ICS950405 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
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