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參數(shù)資料
| 型號： | ICS950223 |
| 英文描述： | Programmable Timing Control Hub? for P4? |
| 中文描述： | 可編程定時控制集線器？為小？ |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 209K |
| 代理商： | ICS950223 |
3
Integrated
Circuit
Systems, Inc.
ICS950223
0496C—05/06/05
Pin Description (Continued)
PIN PIN
PIN
#
NAME
TYPE
25
26
SDATA
SCLK
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Selectable 66.66MHz, 48MHz clock output / Select input for 66.66/48MHz output.
0=48mHz, 1 = 66.66MHz
OUT 3.3V 66.66MHz clock output
PWR Ground pin.
OUT 3.3V 66.66MHz clock output
OUT 3.3V 66.66MHz clock output
PWR Power pin for the 3V66 clocks.
PWR Ground pin.
PWR 3.3V Analog Power pin for Core PLL
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
PWR Ground pin for the CPU outputs
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
PWR Supply for CPU clocks, 3.3V nominal
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
PWR Ground pin for the CPU outputs
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
PWR Supply for CPU clocks, 3.3V nominal
PWR Ground pin for the REF outputs.
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz
reference clock.
27
3V66_3_48MHz/Sel66_48#**
I/O
28
29
30
31
32
33
34
3V66_2
GND
3V66_1
3V66_0
VDD3V66
GND
AVDD
35
IREF
OUT
36
GNDCPU
37
CPUCLKC1
OUT
38
CPUCLKT1
OUT
39
VDDCPU
40
CPUCLKC0
OUT
41
CPUCLKT0
OUT
42
PD#*
IN
43
GNDCPU
44
CPUCLKC2
OUT
45
CPUCLKT2
OUT
46
47
VDDCPU
GNDREF
48
REF0/MULTSEL0**
I/O
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive
DESCRIPTION
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| ICS950227 | Programmable Timing Control Hub for P4 |
| ICS950401 | AMD - K8TM System Clock Chip |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS950227 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for P4 |
| ICS9502P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| ICS950401 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8TM System Clock Chip |
| ICS950402 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
| ICS950402YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K8 System Clock Chip |
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