參數(shù)資料
型號: ICS950223
英文描述: Programmable Timing Control Hub? for P4?
中文描述: 可編程定時控制集線器?為???
文件頁數(shù): 10/24頁
文件大?。?/td> 209K
代理商: ICS950223
10
Integrated
Circuit
Systems, Inc.
ICS950223
0496C—05/06/05
I
2
C Table: Frequency Select Register
Bit 7
FS Source
Frequency H/W IIC
Select
RW
Latch Inputs
IIC
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS6
FS5
FS4
FS3
FS2
FS1
FS0
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
I
2
C Table: Spreading and Device Behavior Control Register
Bit 7
Bit 6
SS1
SS0
Spread Select 1
Spread Select 0
RW
RW
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDS_Status
Reserved
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
WD Soft Alarm Status
Reserved
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
Normal
-
Disable
Disable
Disable
Alarm
-
Enable
Enable
Enable
0
1
1
1
1
SS_EN
Spread Enable Control
RW
OFF
Control Function
Type
0
1
1
PWD
0
See Table 1: QuadRom
Frequency Selection Table
PWD
See Table 2: Spread
Spectrum Table
ON
1
Name
Type
-
-
-
-
Byte 0
-
-
-
Pin #
Control Function
Name
-
-
45/44
38/37
41/40
-
-
Byte 1
Pin #
Bit 5
-
Table2: Spread Spectrum Select
SS1
(Byte 1 bit 7)
0
SS0
(Byte 1 bit 6)
0
0.35%
Spread 1
0
1
0.50%
Spread 2
1
0
0.75%
Spread 3
1
1
1.00%
Spread 4
Spread %
Note
I
2
C Table: Output Control Register
Bit 7
AEN#
3V66/PCI Freq Source
Select
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
CPU_PLL
Sync
Disable
Disable
Disable
Disable
Disable
Disable
Disable
FIX_PLL
Async
Enable
Enable
Enable
Enable
Enable
Enable
Enable
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK9
PCICLK8
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
PWD
12
11
10
Name
Control Function
Type
0
17
16
15
14
-
Byte 2
Pin #
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