
11
Integrated
Circuit
Systems, Inc.
ICS950223
0496C—05/06/05
I
2
C Table: Output Control Register
Bit 7
Bit 6
Bit 5
24_48MHz
48MHz
GR_EN
Output Control
Output Control
Geashift Reset Enable
24_48 Frequency H/W
/ IIC Select
Sel24_48
Output Control
Output Control
Output Control
RW
RW
RW
Disable
Disable
ON
Enable
Enable
OFF
1
1
0
Bit 4
24_48 FS Source
RW
Latch Inputs
IIC
0
Bit 3
Bit 2
Bit 1
Bit 0
FS 24_48
PCICLK2
PCICLK1
PCICLK0
RW
RW
RW
RW
24MHz
Disable
Disable
Disable
48MHz
Enable
Enable
Enable
0
1
1
1
I
2
C Table: Output Control Register
Bit 7
66_48 FS Source
66_48 Frequency H/W
/ IIC Select
Sel66_48#
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
Latch Inputs
IIC
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS 66_48#
3V66_0
3V66_1
REF0
REF1
3V66_3
3V66_2
RW
RW
RW
RW
RW
RW
RW
48MHz
Disable
Disable
Disable
Disable
Disable
Disable
66.66MHz
Enable
Enable
Enable
Enable
Enable
Enable
0
1
1
1
1
1
1
I
2
C Table: 3V66 & PCICLK Asynchronous Frequency Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N PLL2 Div0
N PLL2 Div1
N PLL2 Div2
N PLL2 Div3
N PLL2 Div4
N PLL2 Div5
N PLL2 Div6
N PLL2 Div7
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
I
2
C Table: Read Back Register
Bit 7
WDHRB
WD Hard Alarm Status
Read back
Sel48_24# Read Back
Sel66_48# Read Back
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
R
-
-
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEL48_24RB
SEL66_48RB
FS4RB
FS3RB
FS2RB
FS1RB
FS0RB
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
-
-
-
-
-
PWD
The decimal
representation of N
PLL2 Div (0:7) + 8 is
equal to VCO divider
value for PLL2.
-
-
-
Name
Control Function
Type
0
-
-
-
-
8
7
6
Byte 4
Pin #
Type
0
1
PWD
Control Function
Control Function
Type
0
1
0
1
PWD
1
PWD
23
22
-
Control Function
Byte 3
Pin #
Name
-
-
Name
-
-
31
30
48
1
27
28
-
Byte 5
Pin #
Byte 6
Pin #
Name
Type
-
-
-
-
-
-
-
-