參數(shù)資料
型號(hào): ICS950223
英文描述: Programmable Timing Control Hub? for P4?
中文描述: 可編程定時(shí)控制集線器?為???
文件頁數(shù): 14/24頁
文件大小: 209K
代理商: ICS950223
14
Integrated
Circuit
Systems, Inc.
ICS950223
0496C—05/06/05
I
2
C Table: Output Divider Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
CPUCLK [1:0] divider
ratio can be configured
via these 4 bits
individually.
See Table 3: Divider Ratio
Combination Table
-
-
-
-
Type
0
1
PWD
CPUCLK2 divider ratio
can be configured via
these 4 bits individually.
Byte 15
Pin #
Name
Control Function
See Table 3: Divider Ratio
Combination Table
Table 3: CPU, AGP and PCI Divider Ratio Combination Table
Bit
00
01
10
11
MSB
8
1
2
4
00
0
2
100
4
1000
8
1100
16
01
1
3
101
6
1001
12
1101
24
10
10
5
110
10
1010
20
1110
40
11
11
7
111
14
1011
28
1111
56
LSB
Address
Div
Address
Div
Address
Div
Address
Div
Divider (3:2)
D
I
2
C Table: Output Divider Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66 Div3
3V66 Div2
3V66 Div1
3V66 Div0
3V66 Div3
3V66 Div2
3V66 Div1
3V66 Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
I
2
C Table: Output Divider Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66INV
3V66INV
CPUINV
CPUINV
PCI Div3
PCI Div2
PCI Div1
PCI Div0
3V66[3:2] Phase Invert
3V66[1:0] Phase Invert
CPU Phase Invert
CPU Phase Invert
RW
RW
RW
RW
RW
RW
RW
RW
Default
Default
Default
Default
Inverse
Inverse
Inverse
Inverse
X
X
X
X
X
X
X
X
PWD
-
-
-
-
PCI divider ratio can
be configured via these
4 bits individually.
See Table 3: Divider Ratio
Combination Table
Name
Control Function
Type
0
-
-
-
-
3V66 [1:0] divider ratio
can be configured via
these 4 bits individually.
See Table 3: Divider Ratio
Combination Table
1
Type
0
1
PWD
Byte 16
Pin #
Name
Control Function
-
-
-
-
3V66 [3:2] divider ratio
can be configured via
these 4 bits individually
See Table 3: Divider Ratio
Combination Table
-
-
-
-
Byte 17
Pin #
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