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參數(shù)資料
| 型號： | ICS1893AFLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 55/136頁 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893AFLF 800-2353-5 ICS1893AFLF-ND |
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Chapter 6
Interface Overviews
ICS1893AF, Rev. D 10/26/04
October, 2004
25
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
6.1
MII Data Interface
The ICS1893AF’s MAC Interface is the Medium Independent Interface (MII) operating at either 10 Mbps or
100 Mbps. The ICS1893AF MAC/Repeater Interface is configured for the MII Data Interface mode, data is
transferred between the PHY and the MAC as framed, 4-bit parallel nibbles. In addition, the interface also
provides status and control signals to synchronize the transfers.
The ICS1893AF provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit
and a receive data path to synchronously exchange 4 bits of data (that is, nibbles).
The ICS1893AF’s MII transmit data path includes the following:
– A data nibble, TXD[3:0]
– A transmit data clock to synchronize transfers, TXCLK
– A transmit enable signal, TXEN
– A transmit error signal, TXER
The ICS1893AF’s MII receive data path includes the following:
– A separate data nibble, RXD[3:0]
– A receive data clock to synchronize transfers, RXCLK
– A receive data valid signal, RXDV
– A receive error signal, RXER
Both the MII transmit clock and the MII receive clock are provided to the MAC/Reconciliation sublayer by
the ICS1893AF (that is, the ICS1893AF sources the TXCLK and RXCLK signals to the MAC/repeater).
Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL).
The ICS1893AF is fully compliant with these definitions and sources both of these signals to the
MAC/repeater. When operating in:
Half-duplex mode, the ICS1893AF asserts the Carrier Sense signal when data is being either transmitted
or received. While operating in half-duplex mode, the ICS1893AF also asserts its Collision Detect signal
to indicate that data is being received while a transmission is in progress.
Full-duplex mode, the ICS1893AF asserts the Carrier Sense signal only when receiving data and forces
the Collision Detect signal to remain inactive.
As mentioned in Section 5.1.1.3, “Hot Insertion”, the ICS1893AF design allows hot insertion of its MII. That
is, it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this
functionality, the ICS1893AF isolates its MII signals and tri-states the signals on all Twisted-Pair Transmit
pins (TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the
ICS1893AF enables its MII and enables its Twisted-Pair Transmit signals.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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