參數資料
型號： ICS1893AFLF
廠商： IDT, Integrated Device Technology Inc
文件頁數： 1/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應商設備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFLF
800-2353-5
ICS1893AFLF-ND
ICS1893AF, Rev. F 05/13/10
Octobe
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
Integrated Circuit Systems, Inc.
3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893AF
Document Type:
Data Sheet
Document Stage: Release
Features
Single 3.3V power supply
Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
DSP-based baseline wander correction to virtually
eliminate killer packets
Low-power, 0.35-micron CMOS (typically 400 mW)
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
10Base-T and 100Base-TX IEEE 802.3 compliant
Clock or crystal supported
Media Independent Interface (MII) supported
Managed or Unmanaged Applications
10M or 100M Half and Full Duplex Modes
Auto-Negotiation with Parallel detection for Legacy
products
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
Loopback mode for Diagnostic Functions
Small footprint 48-pin 300 mil SSOP package. Available in
Industrial Temperature and Lead Free packaging.
General
The ICS1893AF is a lower cost, re-packaged version of the
ICS1893Y-10. The ICS1893AF is a fully integrated, Physical
Layer device (PHY) that is compliant with both the 10Base-T
and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC
8802-3. The ICS1893AF uses the same proven silicon as
the ICS1893Y-10 but offers a lower cost solution by using a
lower cost 300 mil. 48-lead SSOP package.
The ICS1893AF uses the same twisted-pair transmit and
receive circuits as the ICS1893Y-10, and the same
recommended board layout techniques apply to the
ICS1893AF.
The ICS1893AF is intended for Node applications using the
standard MII interface to the MAC.
All differences in the ICS1893AF / ICS1893Y-10 Feature Set
are listed in the Comparison Table on page 14.
Clock
Power
LEDs and PHY
Address
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
Integrated
Switch
MII
Extended
Register
Set
Interface
MUX
ICS1893AF Block Diagram
PCS
Framer
CRS/COL
Detection
Parallel to Serial
4B/5B
Auto-
Negotiation
10Base-T
100Base-T
TP_PMD
MLT-3
Stream Cipher
Adaptive Equalizer
Baseline Wander
Correction
PMA
Clock Recovery
Link Monitor
Signal Detection
Error Detection
Low-Jitter
Clock
Synthesizer
Configuration
and Status
10/100 MII
MAC
Interface
MII Serial
Management
Interface
相關PDF資料
PDF描述
VE-JNN-MY-F2 CONVERTER MOD DC/DC 18.5V 50W
ADCMP606BKSZ-R2 IC COMP TTL/CMOS 1CHAN SC70-6
VE-JNM-MY-F4 CONVERTER MOD DC/DC 10V 50W
MAX976EUA+ IC COMPARATOR DUAL 8-UMAX
ISL98003INZ-110 IC AFE 3CH 8BIT 110MHZ 80EPTQFP
相關代理商/技術參數
參數描述
ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數:2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數:2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AG 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*