- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄10742 > ICS1893AFLF (IDT, Integrated Device Technology Inc)PHYCEIVER LOW PWR 3.3V 48-SSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS1893AFLF |
| 廠(chǎng)商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 44/136頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類(lèi)型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 1893AFLF 800-2353-5 ICS1893AFLF-ND |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)當(dāng)前第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)
Chapter 3
Typical ICS1893AF Applications
ICS1893AF, Rev. D 10/26/04
October, 2004
15
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
– Hardwired for Node configuration (NOD/REP pin removed, tied internally to VSS). Node
configuration enables the 10M SQE test default setting and causes CRS to be asserted for either
transmit or receive activity in half duplex, or for just receive activity when in full duplex.
– Hardwired for Software mode (HW/SW pin removed, tied internally to VDD).
– Hardwired for MII interface only. (MII/SI pin removed, tied internally to VSS). In this configuration the
10baseT serial and 100baseTX 5 bit symbol interfaces are NOT supported. Applications requiring
these interfaces should use ICS1893Y-10.
In the software control configuration the 10/100, DPXSEL and ANSEL pins are outputs.
– DPXEL pin is not brought out.
– ANSEL pin is not brought out.
– 10/100 pin is brought out to indicate 100M operation. Some applications use this output to drive an
LED indicating 100M operation.
Pins LSTA (link status) and LOCK (rec. PLL locked) are not brought out.
– LSTA and LOCK provided redundant information already available with the P2LI pin. P2LI indicates
the Link is valid.
Input pin TXER is removed and tied low inside the package. The TXER function is still available by using
the Extended Control Register Reg 16 Bit 2. Most applications tied the TXER pin to VSS.
3.2
ISC1893AF Shared Features
The same silicon die is used in the ICS1893AF and ICS1893Y-10
– Only the package type is different.
The ICS1893AF offers the same.35
3.3V low power operation.
Parametric specifications and timing diagrams are the same as ICS1893Y-10.
Both the ICS1893Y-10 and the ICS1893AF incorporate Digital Signal Processing in their PMD Sub layer,
thereby allowing them to transmit and receive data with Unshielded Twisted Pair (UTP) Category 5
cables up to 150 meters in length. In addition, this ICS-patented technology enables the ICS1893Y-10
ICS1893AF to address the effects of Baseline Wander correction.
Both ICS1893AF and ICS1893Y-10 have improved 10Base-T Squelch operation.
The ICS1893AF uses the same twisted pair transmitter and receive circuits and therefore the same
recommended board layout techniques apply.
Both share improved transmit circuits resulting in a decrease in the magnitude of the 10Base-T harmonic
content generated during transmission (reference ISO/IEC 8802-3: 1993 Clause 8.3.1.3).
Both use digital PLL technology resulting in lower jitter and improved stability.
The MDIO Maintenance interface with the MDIO and MDC pins along with all internal registers are
preserved in the ICS1893AF. This enables software configuring for FD/HD, 10Base-T, 100Base-TX and
Auto-Negotiation to be configurable by the MDIO maintenance interface. Default setting is
Auto-Negotiation Enable. All register settings are the same as in the ICS1893AF datasheet.
The ICS1893AF preserves the dual-purpose LED/Phy Address control pins as in the ICS1893Y-10. The
captured address seeds the scrambler for lower EMI in for multiple Phy applications.
All Auto-Negotiation features are preserved in the ICS1893AF. The reset default mode is A_N enabled.
The A_N parallel detect feature is preserved for legacy interoperability.
Both support Management Frame (MF) Preamble Suppression.
Both support backward compatibility with the ICS1890 Management Registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-JNN-MY-F2 | CONVERTER MOD DC/DC 18.5V 50W |
| ADCMP606BKSZ-R2 | IC COMP TTL/CMOS 1CHAN SC70-6 |
| VE-JNM-MY-F4 | CONVERTER MOD DC/DC 10V 50W |
| MAX976EUA+ | IC COMPARATOR DUAL 8-UMAX |
| ISL98003INZ-110 | IC AFE 3CH 8BIT 110MHZ 80EPTQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。