參數(shù)資料
型號(hào): IC42S32200
英文描述: RES 1M-OHM 1% 0.1W 100PPM THICK-FILM SMD-0603 5K/REEL-7IN-PA
中文描述: 為512k字× 32位× 4銀行(64兆位)同步動(dòng)態(tài)RAM
文件頁(yè)數(shù): 28/62頁(yè)
文件大?。?/td> 900K
代理商: IC42S32200
IC42S32200
IC42S32200L
28
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Figure 5.Self Refresh Entry &Exit Cycle
Note:To Enter SelfRefresh Mode
1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle.
2. After 1 clock cycle,all the inputs including the system clock can be don ’t care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays “l(fā)ow”.
Once the device enters SelfRefresh mode,minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
4. System clock restart and be stable before returning CKE high.
5. Enable CKE and CKE should be set high for minimum time of tSRX.
6. CS#starts from high.
7. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
8. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh.
CLK
CKE
CS#
RAS#
CAS#
BS0,1
A0-A9
WE#
DQM
DQ
*Note 1
*Note 2
t
IS
*Note 3
*Note 4
t
RC(min)
*Note 7
*Note 5
*Note 6
*Note 8
*Note 8
Hi-Z
Hi-Z
SelfRefresh Enter
SelfRefresh Exit
Auto Refresh
SRX
t
PDE
T0
T2
T1
T3
T4
T5
T6
T7
T9
T8
T12
T11
T10
T14
T13
T15
T16
T17
T18
T19
相關(guān)PDF資料
PDF描述
IC42S32200L 512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S32202L-8BIG 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
IC42S32202-7B 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
IC42S32202-7BI 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
IC42S32202-7T 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
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