參數資料
型號: IC42S16800L-8TIG
英文描述: 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 4(2)M中的x 8(16)位× 4銀行(128 - Mbit的)同步動態(tài)RAM
文件頁數: 9/69頁
文件大?。?/td> 1118K
代理商: IC42S16800L-8TIG
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
9
AC ELECTRICAL CHARACTERISTICS
(At V
DD
= V
DDQ
= 3.3 ± 0.3V, V
SS
= V
SSQ
= 0V , unless otherwise note
d
)
-6
-7
-8
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
CK
3
t
CK
2
t
AC
3
t
AC
2
t
CH
t
CL
t
CKE
t
CKH
t
AS
t
AH
t
CMS
t
CMH
t
DS
t
DH
t
OH
3
t
OH
2
t
LZ
t
HZ
t
RC
t
RAS
t
RCD
t
RP
t
RRD
t
T
t
RSC
t
PDE
t
SRX
t
DPL
t
DAL
t
REF
CLK Cycle Time
CL= 3
CL= 2
CL= 3
CL= 2
6
5.4
5.4
5.4
100K
10
64
7.5
10
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.7
3
0
2.7
67.5
45
20
20
15
1
15
7.5
7.5
15
35
5.4
6
5.4
100K
10
64
8
10
3
3
2
1
2
1
2
1
2
1
3
3
0
3
70
50
20
20
20
1
20
10
10
16
36
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
7.5
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.7
2.7
0
2.7
60.0
42
18
15
12
1
12
6
6
12
27
CLK to valid output delay
(1)
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold time
(1)
CL= 3
CL= 2
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
ROW active time
RAS
to
CAS
delay
Row precharge time
Row active to active delay
Transition time
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Data in to Precharge
Data in to Active/Refresh Delay Time
Refresh Time
100K
10
64
Notes:
1.
if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
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